Analog-to-Digital Converter (ADC) Sampling

Resolution is the number of discrete digital values an ADC can produce over its input range, expressed in bits. It defines the smallest detectable change in the analog input voltage, known as the Least Significant Bit (LSB) voltage. A higher resolution provides finer granularity but requires more processing and memory.

• Formula: LSB Voltage = (Vref) / (2^N), where N is the resolution in bits.
• Example: A 12-bit ADC with a 3.3V reference can distinguish 4096 levels, with an LSB of ~0.8mV.
• TinyML Impact: Higher resolution increases data precision but also the size of the raw data buffer, affecting memory usage and potential wireless transmission costs.

The sampling rate or sampling frequency (Fs) is the number of samples an ADC takes per second, measured in samples per second (SPS) or Hertz (Hz). It must be high enough to capture the signal's highest frequency component according to the Nyquist-Shannon theorem.

• Nyquist Criterion: Fs must be > 2 * Fmax to avoid aliasing.
• Oversampling: Sampling at a rate much higher than Nyquist can improve resolution and reduce noise through digital filtering.
• TinyML Impact: Sets the upper limit on the frequency content of signals that can be analyzed (e.g., audio, vibration). Higher rates increase power consumption and data throughput, directly impacting system duty cycle and battery life.

Signal-to-Noise Ratio (SNR) measures the ratio of the power of the fundamental input signal to the power of all noise sources (excluding harmonics), typically expressed in decibels (dB). Effective Number of Bits (ENOB) is a derived metric that indicates the ADC's actual resolution in the presence of noise and distortion.

• Relationship: ENOB = (SNR - 1.76 dB) / 6.02 dB.
• Implication: A 12-bit ADC with an ENOB of 10.5 bits performs, in practice, closer to an ideal 10.5-bit converter.
• TinyML Impact: A low ENOB means useful signal information is lost in noise, degrading model input quality. Careful PCB layout, power supply filtering, and oversampling are used to maximize ENOB in embedded systems.

The input voltage range defines the minimum and maximum analog voltages the ADC can accurately convert. This range is set by the reference voltage (Vref), which can be internal to the MCU, external, or derived from the supply voltage (AVDD).

• Types: Single-ended (0V to Vref) or differential (±Vref).
• Gain: Programmable Gain Amplifiers (PGAs) can scale small sensor signals (e.g., from a microphone or thermocouple) to better utilize the ADC's full input range.
• TinyML Impact: Matching the sensor's output swing to the ADC's input range maximizes dynamic range and resolution. Using a stable, low-noise external voltage reference is critical for high-precision measurements.

Conversion time is the time required for the ADC to perform a single complete sample conversion. Throughput rate is the maximum sustained sampling rate, which is the inverse of the total time per sample (conversion time + acquisition/settling time).

• Acquisition Time: The time allowed for the internal sample-and-hold capacitor to charge to the input voltage.
• Trade-offs: Higher resolution and accuracy often require longer conversion times, reducing maximum throughput.
• TinyML Impact: Determines the real-time capability of the system. For continuous sampling, the ADC throughput must meet or exceed the application's required sampling rate. Power consumption is often proportional to the active sampling rate.

ADC power consumption varies dramatically based on resolution, sampling rate, and architecture (e.g., SAR, Sigma-Delta). MCU ADCs often support multiple operating modes to optimize energy use.

• Modes: Single-conversion, continuous conversion, low-power, and high-speed modes.
• Duty Cycling: A core TinyML technique where the ADC is powered on only for short bursts to take samples, then powered down to save energy.
• TinyML Impact: For battery-powered devices, ADC power is a significant portion of the total budget. Selecting the appropriate mode and minimizing active sampling time through intelligent triggering (e.g., from a wake-up threshold) is essential for achieving multi-year battery life.

The sampling rate is a primary driver of system power. Higher rates provide better temporal resolution but force the ADC, sensor, and microcontroller into more active cycles. Key considerations include:

• Nyquist-Shannon Theorem: Sample at least twice the signal's highest frequency of interest.
• Oversampling: Can improve Signal-to-Noise Ratio (SNR) but at a linear power cost.
• Duty Cycling: Sample in bursts at the required rate, then put the ADC and sensor into a low-power sleep mode. For a 100 Hz signal, sampling at 200 Hz with a 5% duty cycle is far more efficient than continuous sampling.

ADC resolution, measured in bits, determines the smallest detectable voltage change and the system's dynamic range. A 12-bit ADC on a 3.3V reference has an LSB (Least Significant Bit) of ~0.8mV. Trade-offs are:

• Higher Resolution (e.g., 16-bit): Captures finer signal details and a wider range between noise floor and saturation, but increases conversion time, power, and data size.
• Lower Resolution (e.g., 8-bit): Saves power and memory but quantizes the signal more coarsely, potentially losing critical features for the ML model.
• Match to Sensor Noise: There's no benefit to an ADC resolution finer than the inherent noise of the sensor itself.

Raw sensor outputs often require conditioning before ADC sampling to ensure signal integrity and prevent artifacts.

• Anti-Aliasing Filter (AAF): A mandatory low-pass analog filter before the ADC. It removes frequency components above the Nyquist frequency to prevent aliasing, where high frequencies appear as false low frequencies. On tiny devices, this is often a simple passive RC filter.
• Amplification/Attenuation: Scaling the signal to match the ADC's input voltage range (e.g., 0-3.3V) maximizes use of its dynamic range.
• Bypass Capacitors: Placed near the ADC pins to stabilize the reference voltage and reduce noise from the power supply.

The ADC is the start of an on-device data pipeline with severe SRAM and compute limits.

• Buffer Management: Samples are often streamed into a small, fixed circular buffer in SRAM. Its size is a trade-off between capturing enough context for the ML model and available memory.
• Direct Memory Access (DMA): Using DMA allows the ADC to write samples directly to memory without CPU intervention, freeing the core for feature extraction or inference, saving significant power.
• On-the-Fly Feature Extraction: To avoid storing raw samples, compute features (like RMS, ZCR) in the interrupt service routine as data arrives, drastically reducing memory footprint.

ADC output format must align with the quantized input expected by the TinyML model. Modern practice involves co-designing the sampling parameters with the model training.

• Native ADC Format: Many MCU ADCs output unsigned 12-bit integers. The model's input tensor should be quantized to match this (e.g., uint8 or int16).
• Quantization-Aware Training (QAT): Train the model with simulated quantization, including the ADC's effective bit depth and noise, making it robust to the actual hardware's signal fidelity.
• Calibration Offsets: Incorporate sensor and ADC gain/offset errors into the model's preprocessing normalization step, often determined during a one-time factory calibration.

TinyML devices operate in electrically noisy environments (motors, radios). ADC readings are susceptible, requiring mitigation.

• Reference Voltage Stability: A noisy Vref introduces error in every conversion. Use a dedicated, low-noise voltage reference IC or the MCU's internal bandgap reference if precision is critical.
• Oversampling & Averaging: Taking 4x oversamples and averaging reduces uncorrelated noise by 1 bit (6 dB SNR improvement), effectively increasing resolution at the cost of time and power.
• Spatial Averaging: If multiple identical sensors exist, averaging their ADC readings reduces noise.
• Spectral Analysis: Understanding the noise floor via an FFT can inform optimal filter design and sampling rate choices.

The Nyquist rate is the minimum sampling frequency required to perfectly reconstruct a continuous, bandlimited signal from its discrete samples. It is defined as twice the highest frequency component present in the analog signal. Sampling below this rate causes aliasing.

• Core Principle: For a signal with a maximum frequency of f_max, the Nyquist rate is 2 * f_max.
• Practical Implication: Dictates the minimum ADC sampling speed needed for a given sensor bandwidth.
• Example: To accurately digitize an audio signal containing frequencies up to 20 kHz, the ADC must sample at least at 40 kSPS (kilo-samples per second).

Aliasing is a distortion artifact that occurs when a continuous signal is sampled at a rate lower than the Nyquist rate. High-frequency components are misrepresented as lower, false frequencies in the digitized signal, irreversibly corrupting the data.

• Visual Analogy: The "wagon wheel effect" in film, where a spinning wheel appears to rotate backwards.
• Consequence: Makes true signal frequencies indistinguishable from alias frequencies, ruining analysis.
• Prevention: Requires the use of an anti-aliasing filter (a low-pass analog filter) before the ADC to remove frequencies above half the sampling rate.

An anti-aliasing filter is a low-pass analog filter placed immediately before an ADC's input. Its sole purpose is to attenuate frequency components above the Nyquist frequency (half the sampling rate) to prevent aliasing.

• Type: Typically an active or passive RC filter or a more sophisticated Sallen-Key design.
• Key Specification: Its roll-off characteristic determines how sharply it attenuates unwanted high frequencies.
• Design Trade-off: A steeper roll-off (higher-order filter) provides better alias rejection but can introduce phase distortion and requires more components.

Quantization is the process performed by the ADC of mapping the continuous amplitude of each sample to the nearest discrete level defined by its bit depth. This introduces quantization error, a fundamental source of noise.

• Governed by Bit Depth: An N-bit ADC has 2^N discrete quantization levels.
• Error Range: The quantization error for a sample is within ±½ LSB (Least Significant Bit).
• Signal-to-Quantization-Noise Ratio (SQNR): A key metric, approximately 6.02N + 1.76 dB for a full-scale sinusoidal input.
• Example: A 12-bit ADC quantizes a sample into one of 4096 possible values.

A Sample-and-hold (S/H) circuit is a critical analog front-end component of an ADC. It captures (samples) the instantaneous voltage of a fast-changing analog signal and holds it constant for the duration of the ADC's conversion cycle.

• Function: Enables the ADC to convert a stable voltage, as the input signal may change during conversion.
• Key Parameters: Aperture time (time to acquire the sample), settling time, and droop rate (voltage decay during hold).
• Impact: Imperfections in the S/H circuit (e.g., aperture jitter) directly limit the ADC's effective resolution and maximum input frequency.

Effective Number of Bits (ENOB) is a practical performance metric for an ADC that accounts for all non-ideal factors (noise, distortion, jitter) beyond theoretical quantization error. It reports the actual resolution of the converter in a real system.

• Calculation: Derived from the measured Signal-to-Noise-and-Distortion Ratio (SINAD). ENOB = (SINAD - 1.76 dB) / 6.02.
• Significance: Always lower than the ADC's nominal bit depth. A 16-bit ADC might have an ENOB of only 13.5 bits.
• Use Case: The critical specification for system designers determining true dynamic range and precision.