Power Gating

Power gating is implemented using header switches (PMOS transistors between VDD and the virtual VDD rail) or footer switches (NMOS transistors between the virtual GND rail and actual GND).

• Header switches are larger for equivalent resistance but simplify design by keeping the ground network intact.
• Footer switches typically use smaller NMOS transistors, saving area, but require careful management of ground bounce.

The choice affects area, wake-up latency, and noise characteristics of the power-gated domain.

When a block is powered down, its outputs become floating, potentially causing large leakage currents in connected, still-powered blocks. Isolation cells are mandatory interface logic placed at the outputs of a power-gated domain.

• They clamp the output to a known, safe logic level (usually zero) during sleep mode.
• They are always powered by the always-on (AON) domain.
• Failure to implement them correctly can lead to functional failure and increased power consumption, negating the benefits of gating.

A key challenge is preserving the internal state (e.g., register values) of a block when power is removed. State retention techniques address this:

• Retention Registers: Special flip-flops with a secondary, always-powered low-leakage cell that saves state during sleep. They add significant area overhead.
• Software Save/Restore: The processor saves critical registers to always-on memory before shutdown and restores them on wake-up. This increases latency and software complexity.
• The choice is a direct trade-off between wake-up latency, area, and static power savings.

Turning a block back on is not instantaneous and has a power cost.

• Wake-Up Latency: The delay from asserting the wake-up signal to the block being fully operational and stable. It is dominated by the time needed to charge the large virtual power network capacitance through the high-resistance power switch.
• In-Rush Current: A large, instantaneous current spike when the switch first closes, as all discharged capacitances in the block charge simultaneously. This can cause supply voltage droop in other active blocks. Sequenced wake-up of sub-blocks is used to mitigate this.

Power gating can be applied at different levels of granularity, each with distinct control mechanisms:

• Fine-Grained (Cell-Level): Power switches are integrated into standard cells. Controlled by synthesis tools, offering very fine control but high area overhead.
• Coarse-Grained (Block-Level): Large switches gate power to entire macros or processor cores. Controlled by the operating system or firmware via Power Management Unit (PMU) registers. This is the most common approach for TinyML accelerators and MCU peripherals.
• Always-On Domain: A critical co-design concept. A small portion of the chip (PMU, wake-up logic, critical timers) must remain powered to manage the gating of other domains.

Implementing power gating involves significant engineering trade-offs:

• Area Overhead: Power switches, isolation cells, retention registers, and additional control wiring can increase die area by 5-15%.
• Static Power Savings: The primary benefit. By cutting off VDD, subthreshold leakage current is reduced to near zero in the gated block, offering orders of magnitude reduction in idle power.
• Dynamic Power Impact: No impact during active computation. The energy overhead comes from the switching energy of the power gates and the energy cost of saving/restoring state.
• Design Complexity: Introduces new verification challenges for power-up/down sequences, signal isolation, and timing closure across multiple power states.

Modern System-on-Chips (SoCs) for AI implement fine-grained power domains to isolate subsystems. A typical architecture includes:

• Always-On (AON) Domain: A tiny, ultra-low-leakage region powering critical wake-up logic and real-time clocks.
• Sensor Hub Domain: Powers analog front-ends and basic DSP for continuous sensing.
• Main CPU/ML Accelerator Domain: The largest domain, containing the application cores and neural processing unit (NPU), which is power-gated completely between inference bursts.
• Peripheral Domains: Isolated power for radios (BLE, Wi-Fi) and memory blocks. This hierarchy allows the system to power-gate the computationally intensive ML block (consuming milliwatts when idle) while the nano-watt AON domain monitors for trigger events.

This pattern enables ultra-low-power ambient intelligence. A simple, always-powered feature extractor (e.g., computing MFCCs for audio or FFT for vibration) runs on a minimal, non-gated circuit. When extracted features cross a threshold, it triggers a power-on signal to the main power-gated domain containing the full neural network for classification.

Example: A smart wake-word detector. The AON domain runs a low-power analog VAD (Voice Activity Detection). Only upon detecting speech does it power-gate-on the DSP and TinyML model for keyword spotting, achieving an average power draw in the tens of micro-watts.

For larger models that cannot fit entirely in an MCU's SRAM, selective power gating of memory banks is used. The model is partitioned into segments. While one segment is active in SRAM for computation, the Flash memory bank holding the next segment is power-gated. Similarly, in multi-core AI accelerators, individual processing elements (PEs) or systolic array tiles can be power-gated when not in use during a layer's computation, exploiting spatial sparsity in the neural network.

Power gating is most effective as part of a holistic power management unit (PMU) strategy. The standard sequence for entering a low-power state is:

1. Clock Gating: Halt clocks to idle logic (stops dynamic power).
2. Dynamic Voltage and Frequency Scaling (DVFS): Lower voltage/frequency of the still-powered block.
3. Power Gating: If the idle period is predicted to be long enough to amortize the wake-up energy penalty, the footer/header switch opens, cutting all power (eliminates leakage). This creates a power state hierarchy where deeper sleep states have longer wake-up latencies but lower leakage.

In industrial IoT, a vibration sensor powered by a piezoelectric harvester uses aggressive power gating to operate energy-neutrally.

• The high-gain analog sensor amp and a tiny feature extraction core (calculating RMS) run from a nano-power domain.
• Every hour, if the RMS indicates abnormal vibration, it powers on the main Cortex-M4 and SRAM bank.
• A TinyML anomaly detection model (e.g., autoencoder) runs on the full vibration spectrum.
• The result is transmitted via a power-gated BLE radio.
• The entire high-power domain is then shut down, with leakage reduced to pico-amps, allowing operation from intermittent energy sources.

A wildlife camera trap using a CNN for animal classification employs temporal power gating to achieve multi-year battery life.

• A passive infrared (PIR) sensor in the AON domain detects motion.
• This triggers power to the image sensor, ISP, and SRAM.
• A frame buffer is filled, then the image sensor is power-gated.
• The ML accelerator domain is powered on to execute the quantized CNN (e.g., MobileNetV2).
• Only if classification confidence is high is the cellular modem domain powered on to transmit. This orchestration reduces average system current from ~100mA during active inference to <10µA during sleep, dominated by the PIR and AON domain leakage.

Clock gating is a power-saving technique that disables the clock signal to idle sections of a digital circuit. Unlike power gating, which cuts off the power supply entirely, clock gating eliminates dynamic power consumption caused by unnecessary clock toggling but does not reduce static (leakage) power. It is a finer-grained, lower-latency technique often used in conjunction with power gating for hierarchical power management.

• Mechanism: Inserts a gate (e.g., an AND gate) controlled by an enable signal into the clock tree.
• Use Case: Turning off the clock to an unused arithmetic logic unit (ALU) or a memory bank that is not being accessed during a given cycle.

Dynamic Voltage and Frequency Scaling (DVFS) is a run-time power management technique that adjusts a processor's operating voltage and clock frequency in response to real-time computational demand. It exploits the cubic relationship between voltage and dynamic power (P ∝ CV²f). By lowering both voltage and frequency during periods of low workload, DVFS achieves significant energy savings with a graceful performance trade-off.

• Key Relationship: Reduced voltage allows for reduced frequency while maintaining circuit stability.
• TinyML Application: Scaling down the CPU/accelerator frequency during low-priority inference tasks or idle periods between sensor sampling.

Leakage power reduction encompasses a suite of circuit and architectural techniques aimed at minimizing static power dissipation, which is caused by subthreshold and gate leakage currents in transistors. In deep sub-micron process technologies (e.g., below 28nm), leakage becomes the dominant power concern, especially for always-on devices. Power gating is the most aggressive form of leakage reduction.

• Other Techniques: Use of high-threshold voltage (HVT) cells in non-critical paths, multi-threshold CMOS (MTCMOS), and body biasing.
• Importance for TinyML: Critical for extending battery life in devices with long idle periods, such as environmental sensors.

An Always-On (AON) domain is a small, isolated power domain on a system-on-chip (SoC) that remains powered while the main compute cores and other subsystems are power-gated into a deep sleep state. It typically contains ultra-low-power components like a real-time clock (RTC), simple state machines, and interfaces for wake-on-event triggers from sensors or timers.

• Function: Enables always-on sensing and system wake-up management with minimal quiescent current.
• Design Pattern: The AON domain monitors a sensor. When a threshold is crossed, it triggers the power switches to activate the main CPU domain, which runs the full TinyML inference.

The energy-accuracy trade-off defines the fundamental design space in TinyML where reductions in computational cost directly impact model precision. Techniques that save energy—such as quantization, pruning, early exiting, or using smaller models—often result in a decrease in task accuracy. System architects must navigate this Pareto frontier based on application requirements.

• Quantization Example: Using 8-bit integers instead of 32-bit floats reduces memory bandwidth and compute energy but may lower accuracy on sensitive tasks.
• System-Level Decision: Power gating provides energy savings with zero impact on accuracy, as it is purely a hardware management technique applied during idle times.

Wake-on-event is a system power management feature where a device in a deep sleep state (with major domains power-gated) is awakened by a specific external or internal trigger. This enables ultra-low-power always-on capability without requiring the main processor to be active. The trigger is typically handled by the Always-On (AON) domain.

• Event Sources: GPIO pin toggle, analog comparator output, timer interrupt, or a packet from a wake-up radio (WuR).
• TinyML Workflow: A low-power analog front-end or simple digital circuit monitors a sensor (e.g., microphone for a keyword). Upon detecting a potential event, it wakes the main processor, which powers up, runs a full TinyML inference model, and then powers down again.