Battery-Aware Task Mapping

The scheduler continuously monitors the battery's State-of-Charge (SoC)—the remaining capacity as a percentage of its maximum. It uses this data to make task allocation decisions:

• High SoC (>80%): The system can schedule more computationally intensive tasks or use higher-performance cores, as ample energy is available.
• Low SoC (<20%): The scheduler aggressively conserves energy by offloading tasks to the most efficient cores, reducing clock speeds, or deferring non-critical computations. This prevents unexpected shutdowns by ensuring critical functions always have a reserved energy budget.

A battery's internal resistance increases with age, depth of discharge, and temperature. Higher resistance causes greater voltage drop under load, wasting energy as heat. Battery-aware mapping incorporates a model of this resistance to optimize task placement:

• It avoids scheduling high-current bursts (e.g., activating a high-performance CPU core) when resistance is high, as this would inefficiently convert energy to heat.
• Instead, it may spread the same computational workload over a longer period on a more efficient core to reduce the instantaneous current draw, thereby minimizing losses. This modeling is critical for maximizing usable energy from aging batteries.

The algorithm aims to minimize battery degradation to extend the device's functional lifespan. It does this by avoiding scheduling patterns that accelerate wear:

• Minimizing Depth of Discharge (DoD): Prefers frequent, shallow discharge cycles over deep discharges, which are more stressful on battery chemistry.
• Reducing High-Current Stress: Distributes high-compute tasks to prevent sustained high-current draws that degrade capacity faster.
• Temperature Management: May throttle performance or reschedule tasks to prevent operations that would cause excessive battery heating, a major degradation factor. The goal is energy-proportional computing over the device's entire lifetime, not just a single charge cycle.

Modern Systems-on-Chip (SoCs) for edge devices feature heterogeneous cores (e.g., high-performance 'big' cores and ultra-efficient 'LITTLE' cores). Battery-aware mapping dynamically assigns tasks to the optimal core type:

• Latency-Critical Tasks: Mapped to high-performance cores for fast completion, used sparingly when battery state permits.
• Background/Periodic Tasks: Routinely mapped to high-efficiency cores to minimize energy per operation. This allocation is continuously adjusted based on the Energy-Delay Product (EDP) trade-off, current battery health, and task deadlines.

The task mapper does not operate in isolation; it is tightly integrated with the operating system's broader Dynamic Power Management (DPM) framework. It coordinates with:

• Sleep States (C-States): Schedules task batches to create longer, uninterrupted sleep periods for the system, reducing leakage power.
• Dynamic Voltage and Frequency Scaling (DVFS): Recommends voltage/frequency settings for scheduled tasks based on battery condition and deadline.
• Power Gating: Its task allocation decisions inform which entire core or accelerator blocks can be completely powered down (power gated) between scheduled activations. This integration ensures a cohesive, system-wide strategy for energy-constrained scheduling.

The system employs predictive models to forecast near-future workload demands and expected energy harvest (for devices with energy harvesting integration). Using these forecasts, it:

• Creates an Energy Budget: Allocates joules from the current battery state to anticipated tasks.
• Makes Proactive Trade-offs: Decides to process data immediately at higher fidelity or store it and process later at lower fidelity based on predicted future energy availability.
• Ensures Critical Operation: Guarantees that a minimum energy reserve is maintained for essential wake-on-event and always-on domain functions. This transforms scheduling from reactive to proactive, aiming for energy-neutral operation in harvesting scenarios.

A continuous glucose monitor or cardiac patch must operate for weeks on a single charge. Battery-aware mapping schedules high-compute tasks like anomaly detection or signal filtering based on the battery's state-of-charge (SoC) and internal resistance. For example, a full battery can handle intensive Fast Fourier Transform (FFT) analysis, while a depleted battery routes the same sensor stream through a simpler, lower-power thresholding algorithm on an always-on (AON) co-processor. This ensures critical vitals are always monitored, maximizing operational days before recharge.

Wireless vibration sensors on factory equipment are often inaccessible. The scheduler uses a battery degradation model to plan its duty cycle. Key actions include:

• Mapping high-frequency sampling and convolutional neural network (CNN) inference for bearing fault detection to periods of predicted high battery efficiency.
• Deferring non-critical tasks like diagnostic model updates or extended communication sessions when battery internal resistance is high (e.g., in cold temperatures).
• Prioritizing essential heartbeat transmissions to the gateway to maintain network presence, even at very low charge states. This extends deployment life from months to years, reducing maintenance costs.

Soil moisture and climate sensors in remote fields rely on solar harvesting. The mapping algorithm must coordinate with Maximum Power Point Tracking (MPPT). It performs energy-constrained scheduling:

• After a sunny day, the battery is full and efficient. The scheduler maps data fusion and on-device learning tasks for crop disease prediction to the main MCU.
• During cloudy periods, it maps only essential sensing to a near-threshold computing (NTC) core and uses extreme duty cycling for LoRaWAN transmissions.
• It avoids deep discharge cycles known to accelerate battery degradation, preserving total system capacity over multiple seasons.

For a drone, battery state dictates computational capability for navigation. The flight controller's scheduler dynamically maps tasks:

• At mission start (100% SoC): Maps complex SLAM and object avoidance vision transformer models to the primary GPU accelerator.
• At 40% SoC: Re-maps navigation to a simpler, quantized CNN path planner on a high-efficiency neural processing unit (NPU).
• At 15% SoC: Triggers a low-power inference mode, mapping only essential stabilization control to the main CPU and initiating return-to-home on a bare-metal co-processor. This ensures the drone conserves enough energy for a safe landing, not just computation.

Modern smartphones use battery-aware mapping to balance performance and longevity. The operating system scheduler considers battery health index (a measure of degradation). Examples include:

• Mapping intensive tasks like video rendering or AR game physics to the performance CPU cluster only when the battery is healthy and above 30% charge.
• On an aged battery with high internal resistance, it remaps background tasks (photo indexing, cloud sync) to the efficiency cores to reduce voltage droop and prevent sudden shutdowns.
• It may throttle dynamic voltage and frequency scaling (DVFS) peaks for the GPU if the battery temperature is high, directly linking thermal management to task placement.

Autonomous underwater vehicles (AUVs) have fixed, inaccessible battery packs. Mission-critical mapping is essential:

• The scheduler uses a Kalman filter to estimate remaining capacity under varying pressure and temperature.
• It maps high-energy sonar image processing and sensor fusion for seabed mapping to run in bursts during high-efficiency battery phases.
• For long transit segments, it maps navigation to a low-power FPU and puts the main AI accelerator into power-gated sleep.
• If a cell imbalance is detected (a degradation signal), it re-maps all tasks to a reduced voltage domain, sacrificing processing speed for mission completion and safe recovery.

An operating system or runtime technique that allocates computational tasks across processing cores and schedules their execution times to minimize total system energy consumption while meeting performance deadlines. Unlike battery-aware mapping, it typically focuses on instantaneous power, not long-term battery state.

• Key Objective: Minimize energy per workload.
• Common Techniques: Load balancing, frequency scaling, and task consolidation.
• Contrast: Battery-aware mapping incorporates battery chemistry models (e.g., state-of-charge, internal resistance) to maximize total operational cycles before failure.

A hardware-level power management technique that dynamically adjusts a processor's operating voltage and clock frequency based on real-time computational workload demands. It is a foundational mechanism often managed by a battery-aware task mapper.

• Principle: Quadratic reduction in dynamic power with voltage scaling.
• Trade-off: Lower voltage/frequency saves energy but increases task latency.
• Integration: The mapper uses DVFS knobs to execute tasks at the most energy-efficient operating point for the current battery health.

An algorithmic approach that determines the order and timing of task execution on a device with a finite energy budget (e.g., a battery), aiming to complete a set of tasks before the available energy is depleted. It is a critical input to battery-aware mapping.

• Core Problem: Scheduling under a hard energy cap.
• Objective: Maximize completed work or system utility.
• Relation: Battery-aware mapping extends this by treating the battery not as a simple capacitor but as a degradable asset with non-linear discharge characteristics.

A system-level strategy that dynamically controls the power states (e.g., active, idle, sleep, off) of hardware components based on workload predictions and performance requirements. Battery-aware task mapping is a form of DPM applied to computational resource allocation.

• Mechanisms: Putting idle cores to sleep, power-gating unused accelerators.
• Policy: Decides when to transition components between power states.
• Synergy: The mapper provides the workload forecast and task assignments that inform the DPM policy's state transition decisions.

Describes the design space in machine learning systems where reducing computational precision, model size, or activation sparsity saves energy but may also decrease the model's prediction accuracy. Battery-aware mapping must navigate this trade-off.

• Examples: Using an 8-bit quantized model vs. a 32-bit floating-point model.
• Mapper's Role: Can select from multiple model variants (e.g., early-exit networks) of differing accuracy and energy cost based on remaining battery capacity and task criticality.

A key performance-per-watt metric for machine learning, measuring the number of neural network inferences a system can perform per joule of energy consumed. It is the primary benchmark for evaluating the energy efficiency of AI accelerators that a battery-aware mapper targets.

• Calculation: Inferences per second divided by average power (Watts).
• Importance: Directly correlates to device battery life for AI workloads.
• Mapper's Goal: To maximize system-level inference-per-watt over the entire battery discharge cycle, not just at a single operating point.