Low-Precision Training

The dominant industry standard, popularized by frameworks like NVIDIA's Automatic Mixed Precision (AMP). It uses 16-bit floating-point (FP16/BF16) for most operations to accelerate computation and reduce memory usage, while keeping a master copy of weights in 32-bit FP32 to maintain numerical stability during gradient accumulation and optimization steps. Key components include:

• Loss Scaling: Gradients are scaled up before conversion to FP16 to prevent underflow of small values.
• FP32 Master Weights: The optimizer updates these high-precision weights, which are cast to FP16 for the forward/backward pass.
• This technique is foundational for training large models like GPT and Stable Diffusion, providing up to 3x speedup on modern GPUs.

A process where the model is trained with simulated quantization noise, allowing it to learn parameters robust to the precision loss of subsequent integer deployment. Unlike Post-Training Quantization (PTQ), QAT models the effects of rounding and clipping during the training loop.

• Fake Quantization Nodes: Inserted into the computational graph to simulate INT8 (or lower) arithmetic during forward passes.
• Straight-Through Estimator (STE): Allows gradients to bypass the non-differentiable quantization function during backpropagation.
• This technique is critical for achieving high accuracy with INT4 or INT8 models on microcontrollers and NPUs, where PTQ alone causes significant degradation.

A 16-bit floating-point format designed by Google for machine learning. It preserves the 8-bit exponent range of FP32 but truncates the mantissa to 7 bits. This design offers key advantages:

• Dynamic Range: Matches FP32, reducing the risk of overflow/underflow compared to FP16.
• Hardware Efficiency: Requires less memory bandwidth and storage than FP32.
• Simplified Conversion: Truncation from FP32 to BF16 is a simple bitmask operation. BFloat16 is natively supported by Google TPUs, NVIDIA Ampere+ GPUs, and Intel CPUs, making it a standard for distributed training of large models.

An emerging standard for 8-bit floating-point computation, formalized by NVIDIA, Arm, and Intel. It is designed for both training and inference. There are two primary variants:

• E5M2: 5 exponent bits, 2 mantissa bits. Offers a larger dynamic range, suitable for forward propagation and weights.
• E4M3: 4 exponent bits, 3 mantissa bits. Offers higher precision, suitable for gradient computation during backpropagation. FP8 enables entire training pipelines to operate in 8-bit, potentially doubling throughput and halving memory use compared to FP16/BF16, and is supported by NVIDIA's Hopper architecture.

An advanced frontier where the entire training process—forward pass, backward pass, and optimizer updates—is performed using integer arithmetic, eliminating floating-point operations entirely. This is essential for training directly on hardware without FPUs.

• Techniques: Employ integer batch normalization, quantized gradient estimators, and specialized integer-friendly optimizers.
• Formats: Uses INT8, INT4, or non-standard formats like POD (Post-training piecewise linear quantization).
• Use Case: Enables on-device learning and federated learning on extreme edge devices like microcontrollers, ensuring data never leaves the chip.

Low-precision training is enabled by specialized hardware instructions and data formats. Key hardware support includes:

• NVIDIA Tensor Cores: Execute matrix operations on FP16, BF16, TF32, FP8, and INT8 data with high throughput.
• Google TPU Matrix Units: Optimized for BF16 and INT8 operations.
• AMD Matrix Cores (CDNA): Support FP16, BF16, and INT8.
• Apple Neural Engine: Supports 16-bit and 8-bit formats for on-device training. Specialized formats like TF32 (TensorFloat-32) on NVIDIA GPUs bridge the gap between FP32 and BF16 for single-precision accuracy with faster tensor core math.

A training strategy that uses different numerical precisions for different operations or tensors within a single model to optimize the speed-memory-accuracy trade-off. Common patterns include:

• Keeping weights in FP32 for precise weight updates.
• Using FP16 or BF16 for activations and gradients to reduce memory bandwidth.
• Storing optimizer states (like momentum) in lower precision. This is distinct from uniform low-precision training and is heavily utilized in modern frameworks like NVIDIA's Apex AMP to train large models that would otherwise not fit in GPU memory.

A numerical representation system that uses a fixed number of integer bits for the whole number part and a fixed number of fractional bits. It is the integer-based foundation for most quantized inference on microcontrollers (MCUs). Key concepts include:

• Q-format notation (e.g., Q7.8 for 7 integer, 8 fractional bits).
• Managing overflow and underflow through careful scaling.
• While low-precision training often uses floating-point types (FP16/BF16), the resulting models are almost always converted to fixed-point for efficient MCU deployment.

A 16-bit floating-point format designed by Google for machine learning. It retains the same 8-bit exponent range as FP32 but uses only a 7-bit mantissa (vs. FP16's 10-bit). This design makes it highly suitable for low-precision training because:

• It dramatically reduces memory usage compared to FP32.
• Its dynamic range matches FP32, reducing the risk of gradient underflow/overflow that can occur with standard FP16.
• It is natively supported by modern AI accelerators (TPUs, latest GPUs) for accelerated training.

A specific sub-technique within low-precision training focused on reducing the precision of gradients during the backward pass and communication. It is essential for:

• Distributed Training: Compressing gradients before transmission between workers to alleviate network bottlenecks.
• Federated Learning: Where model updates from edge devices must be communicated efficiently.
• Techniques like 1-bit SGD or block-wise quantization are used, often with error feedback mechanisms to preserve convergence accuracy despite the lossy compression.