Channel Search

Channel search is the automated process of determining the optimal number of output channels (filters) for each convolutional layer within a neural network. Its primary objective is to find a Pareto-optimal balance between model accuracy and computational efficiency, directly targeting metrics like parameter count, FLOPs, and memory bandwidth usage. Unlike manual tuning, it systematically explores a vast space of possible widths to discover non-intuitive, highly efficient architectures.

The number of channels is a primary driver of a model's computational footprint. Each search decision has cascading effects:

• Parameter Count: Directly proportional; more channels mean more weights.
• FLOPs: Increases quadratically with channel count in standard convolutions.
• Activation Memory: Determines the size of feature maps stored during inference, critical for SRAM-constrained microcontrollers.
• Data Movement: Heavily influences energy consumption, as moving data between memory and compute units often dominates power use in tinyML deployments.

Effective channel search is inseparable from accurate hardware cost models. The search algorithm uses these models to predict the real-world impact of width choices:

• Lookup Tables (LUTs): Pre-measured latency/energy for each layer type and configuration on target hardware (e.g., ARM Cortex-M).
• Analytical Models: Functions that estimate cost based on operations, memory access patterns, and data reuse.
• Hardware-in-the-Loop Profiling: Directly deploying and measuring candidate sub-networks on the physical device for ground-truth feedback, essential for MCU-NAS.

The channel search space is defined by discrete choices per layer. Common formulations include:

• Layer-wise Multipliers: A base channel count is scaled by a multiplier (e.g., 0.5x, 1x, 1.5x, 2x) for each block.
• EfficientNet-style Compound Scaling: Channels are scaled uniformly by a global coefficient (φ), but hardware-aware search breaks this uniformity.
• Differentiable Relaxation: Channel counts are treated as continuous variables within a supernet, allowing gradient-based optimization via techniques like Gumbel-Softmax sampling.

Channel search is rarely performed in isolation. It is one axis in a multi-dimensional search space that must be co-optimized with:

• Operator Search: Choosing between standard conv, depthwise conv, or pooling.
• Kernel Size Search: Determining filter spatial dimensions (3x3 vs. 5x5).
• Connectivity Search: Deciding skip connections or branching (e.g., for MobileNetV3 or EfficientNet-Lite).
• Quantization-Aware Search (QA-NAS): Ensuring chosen widths remain performant under INT8 or lower precision.

For microcontroller deployment, channel search is paramount due to extreme constraints:

• Memory-Bound Optimization: Search prioritizes architectures that minimize peak activation memory to fit within tiny SRAM (e.g., 256KB).
• Latency Guarantees: Searches under hard latency constraints (e.g., < 100ms) for real-time sensor processing.
• Energy-Aware Search: Models channel count's impact on duty cycling and total system energy consumption.
• Frameworks: Implemented in tools like MCUNet and TinyNAS, which co-design efficient channel configurations with microcontroller memory management.

The Once-For-All framework trains a single supernet that supports elastic width (channels), depth, and kernel size. Channel search is performed by sampling sub-networks with varying numbers of output channels per layer from this supernet without retraining.

• Elastic Channels: The supernet is trained with progressive shrinking, allowing any number of channels (e.g., a multiple of a base number like 16) to be active.
• Zero-Shot Extraction: After supernet training, a hardware-aware search algorithm (e.g., evolutionary search) evaluates thousands of sub-networks with different channel configurations in seconds by leveraging weight sharing.
• Use Case: Ideal for deploying a family of models across diverse microcontroller tiers from a single trained network.

ProxylessNAS directly searches for an optimal architecture on the target task and hardware, eliminating proxy datasets or reduced training epochs. It incorporates channel count as a searchable parameter.

• Direct Hardware Measurement: The search process builds and profiles candidate models with different channel widths directly on the target microcontroller (or an accurate simulator), obtaining true latency and memory readings.
• Gradient-Based Search: It uses a Differentiable Architecture Search (DARTS)-like method where the choice of channel count is relaxed into a continuous, optimizable parameter. The search learns which channel counts contribute most to the objective (accuracy - λ * latency).
• Result: Discovers a single, highly efficient model tailored to a specific device's constraints.

Evolutionary algorithms are a popular search strategy for channel optimization, especially when the search space is large and non-differentiable.

• Population-Based: Maintains a population of candidate architectures (genomes), where each gene can represent the channel count for a specific layer.
• Mutation & Crossover: New candidates are generated by randomly mutating (e.g., increasing/decreasing channels in a layer) or combining parents' channel configurations.
• Fitness Evaluation: Each candidate's fitness is a multi-objective score combining validation accuracy (often estimated via a supernet or zero-cost proxy) and hardware cost (from a hardware cost model). The search evolves towards the Pareto frontier of optimal trade-offs.

This gradient-based method treats channel selection as a categorical choice problem solvable via continuous relaxation.

• Architecture Parameters: For each layer, a set of learnable parameters (alphas) corresponds to different potential channel multipliers (e.g., 0.5x, 1x, 1.5x base channels).
• Continuous Relaxation: During search, the layer's output is a weighted sum of operations with different channel widths. The weights are determined by applying a Gumbel-Softmax trick to the alphas, making the selection differentiable.
• Discretization: After training, the channel count with the highest learned alpha is chosen for the final architecture. This method efficiently navigates the channel search space using gradient descent.

Pioneered by MNasNet, this method integrates a latency constraint directly into the loss function during a differentiable search, making channel choices latency-aware.

• Latency Estimation: A hardware cost model (e.g., a lookup table or small NN) predicts the inference latency of each layer based on its configuration, including input/output channels, kernel size, and stride.
• Multi-Objective Loss: The search optimizes: Loss = CrossEntropyLoss + β * log(Latency(candidate)). The term log(Latency(candidate)) is differentiable with respect to the channel selection parameters.
• Outcome: The search automatically learns to reduce channels in layers that are latency-critical on the target hardware, optimizing the overall network width.

For Microcontroller NAS (MCU-NAS), full training of each candidate is impossible. Zero-cost proxies are used to rapidly score channel configurations based on initial network state.

• Proxies for Trainability: Metrics like gradient norm or synaptic flow (SNIP) are computed after a single batch. Networks with channel configurations leading to higher signal flow are presumed to train better.
• Efficiency Heuristics: Simple hardware-aware heuristics are combined with proxies, e.g., penalizing architectures where the total number of parameters (heavily influenced by channels) exceeds the MCU's flash memory budget.
• Workflow: Generate random channel-width architectures, score them with zero-cost proxies and hardware models, and select the top performers for the full, but short, training cycle. This prunes the search space dramatically.

The search space defines the universe of all possible neural network architectures an algorithm can explore. It is parameterized by variables like:

• Layer types (e.g., convolution, pooling)
• Connectivity patterns (e.g., skip connections)
• Hyperparameters (e.g., number of channels, kernel sizes) Channel search operates within this space, specifically optimizing the width dimension. A well-designed search space balances expressiveness with tractability to enable efficient discovery of high-performing models.

A hardware cost model is a predictive function that estimates key deployment metrics—like latency, energy consumption, and memory usage—for a candidate neural network on specific target hardware. In hardware-aware NAS, this model is integrated into the search objective. For channel search, the cost model predicts how increasing or decreasing the number of output channels in a layer impacts the total operations (FLOPs) and memory footprint on a microcontroller or NPU.

Multi-Objective NAS simultaneously optimizes a neural network across competing goals, such as accuracy, latency, and model size. Channel search is inherently a multi-objective problem: adding channels generally improves representational capacity (accuracy) but increases computational cost and memory (latency/size). The search algorithm must navigate this trade-off to find architectures that best balance these conflicting objectives for the target application.

Once-For-All is a one-shot NAS and training paradigm that decouples training from search. It trains a single, large supernet encompassing many sub-networks of varying depths, widths (channels), and kernel sizes. After training, specialized sub-networks for different hardware constraints can be extracted without retraining. Channel search within an OFA framework involves selecting the optimal channel configuration from this pre-trained supernet for a given latency or memory budget.

A latency constraint is a hard or soft upper bound on the inference time of a model, forcing the NAS algorithm to discover architectures that meet real-time performance requirements. In channel search for microcontrollers, this constraint directly limits how many channels can be used in computationally heavy layers. The search must find the channel configuration that maximizes accuracy without exceeding the strict millisecond-level latency budget of the edge device.

Microcontroller NAS refers to hardware-aware search methods specifically tailored for microcontrollers. It optimizes for extreme constraints:

• Kilobyte-scale RAM/Flash memory
• Microjoule-level energy per inference
• Megahertz-range clock speeds Channel search in this context is exceptionally sensitive, as a single extra channel in a convolutional layer can exceed the available memory budget or break real-time deadlines, making efficient search strategies paramount.