Secure Element

Secure Elements are validated against rigorous international security certification standards. This provides an objective, third-party assessment of their security claims and assurance level.

• Common Criteria (CC): The primary international standard (ISO/IEC 15408). Certifications like CC EAL 4+ or EAL 5+ are common for SEs, indicating evaluation assurance levels.
• FIPS 140-3: U.S. government standard for cryptographic modules. SEs often achieve FIPS 140-3 Level 3 or 4 (hardware security).
• EMVCo Certification: For payment-specific SEs (e.g., in smart cards).
• SESIP (IoT Security Evaluation Standard): A lightweight profile based on Common Criteria, designed for IoT processors and SEs.

The SE operates as a physically and logically separate subsystem from the device's main application processor (the Rich Execution Environment or REE). This isolation is the foundation of its security.

• Dedicated CPU & Memory: Has its own processor, RAM, and persistent storage (EEPROM/Flash), inaccessible to the main host.
• Protected Communication: Interfaces (like I²C, SPI, or ISO 7816) use secure messaging protocols to prevent bus snooping or command injection.
• Defined API: The host application interacts only through a strictly defined, high-level command interface (e.g., GlobalPlatform specifications), never by directly accessing SE memory.

At its core, an SE is a dedicated cryptographic coprocessor with secure key storage. It performs operations internally, ensuring private keys never leave the chip's boundary.

• Hardware Accelerators: For algorithms like AES, SHA-2/SHA-3, ECC (e.g., NIST P-256), and RSA.
• Secure Key Generation & Storage: Contains a True Random Number Generator (TRNG) and protected non-volatile memory for keys. Keys can be marked as non-exportable, making extraction physically impossible.
• Key Usage Enforcement: Policies can be set per key (e.g., 'sign only', 'decrypt only'), preventing misuse even if the host is compromised.

The SE provides a hardware-enforced vault for sensitive data beyond just cryptographic keys. This storage is encrypted and integrity-protected at the hardware level.

• Encrypted Filesystem: Data is stored in an encrypted, access-controlled internal filesystem.
• Integrity Protection: Uses Message Authentication Codes (MACs) or cryptographic counters to detect unauthorized data tampering.
• Anti-Rollback Protection: Maintains secure counters to prevent reverting to older, potentially vulnerable software or data states.

A Secure Element provides a set of standardized security services to the host application, abstracting complex cryptography into simple, secure commands.

• Digital Signature Generation: Creates signatures for device attestation or secure boot verification.
• Secure Boot & Firmware Validation: Can store the root of trust public key and validate the host MCU's firmware image.
• Device Identity & Attestation: Houses a unique device X.509 certificate and can generate attestation reports proving the device's genuine identity and software state.
• Secure Update Management: Can authenticate and decrypt firmware updates delivered via Secure OTA (SOTA) before passing them to the main MCU.

An Integrated Secure Element (iSE) is a dedicated security core fabricated on the same silicon die as the main application microcontroller unit (MCU). This provides the highest level of physical integration and security against bus probing attacks.

• Key Features: Hardware isolation, shared memory protection, and low-latency communication with the main CPU.
• Common Use: Found in modern automotive microcontrollers (e.g., for secure gateway ECUs), high-end IoT sensors, and payment terminals where space and cost are critical.
• Example Chips: Infineon's OPTIGA™ Trust, STMicroelectronics' STSAFE series.

A Discrete Secure Element is a standalone, certified semiconductor chip connected to a host MCU via a serial bus like I²C or SPI. It acts as a dedicated cryptographic coprocessor and secure vault.

• Key Features: Highest certification levels (Common Criteria EAL5+), independent power supply, and robust tamper detection.
• Common Use: Smart cards (SIM, payment), hardware authentication tokens (YubiKey), medical devices, and as a companion chip to enhance the security of a standard MCU.
• Example Chips: NXP's A100x/SE050 family, Microchip's ATECC608.

The Universal Integrated Circuit Card (UICC), commonly the Subscriber Identity Module (SIM) card, is a standardized, removable Secure Element defined by the GlobalPlatform and ETSI specifications.

• Key Features: Portable, personalized, and managed remotely via Over-The-Air (OTA) protocols.
• Common Use: Primary use is in cellular networks for subscriber authentication (Ki key storage). Also used for secure mobile payments (e.g., NFC-based Google Wallet/Apple Pay), digital identity, and IoT device credential provisioning.
• Standards: Java Card OS runs on these chips to host multiple secure applications (applets).

An Embedded Secure Element (eSE) is a discrete Secure Element chip that is permanently soldered onto a device's main circuit board, typically in a system-on-module (SoM) design.

• Key Features: Non-removable, offers a balance between the high security of a discrete chip and the integration of an iSE.
• Common Use: Smartphones and tablets (for secure biometric data storage and payment), set-top boxes, gaming consoles, and industrial gateways where the device itself is the trusted entity.
• Management: Often provisioned with keys during manufacturing and managed via TEE-based APIs.

This implementation incorporates a Secure Element into a MicroSD card form factor, combining secure storage with removable, high-capacity memory.

• Key Features: Portable security with mass storage. The Secure Element partition is logically and physically separated from the user-accessible flash memory.
• Common Use: Secure boot for single-board computers (e.g., Raspberry Pi), portable medical data records, field-updatable secure logging for industrial equipment, and as a hardware token for laptop authentication.
• Example: Swissbit's iShield series.

A secure, isolated area of a main processor (like an application CPU) that provides protected execution. Unlike a discrete Secure Element chip, a TEE uses hardware-enforced isolation (e.g., ARM TrustZone) within the same processor to create a 'secure world.' It's used for mobile payments (Google Wallet), biometric processing, and DRM. A TEE offers strong software isolation, while a Secure Element provides higher physical tamper resistance.

A hardware security primitive that exploits microscopic, random variations in silicon manufacturing to create a unique, device-specific 'fingerprint.' This fingerprint acts as a root key for cryptographic operations. PUFs are often integrated inside a Secure Element to generate and reconstruct keys without storing them in non-volatile memory, providing inherent resistance to physical probing and key extraction attacks.

A hardware-enforced verification chain that ensures a device only executes cryptographically signed and authenticated code from the moment of power-on. The process typically begins in an immutable hardware root of trust (like a Secure Element or boot ROM), which verifies the next stage bootloader. This establishes a chain of trust for the entire software stack, preventing the execution of malicious or tampered firmware on the main microcontroller.

A class of cryptographic algorithms optimized for constrained devices like microcontrollers. These algorithms (e.g., Ascon, ChaCha20-Poly1305) are designed for small code size, low RAM usage, and minimal power consumption—critical for Secure Elements in TinyML devices. Standards like NIST Lightweight Cryptography ensure these algorithms provide robust security (confidentiality, integrity) while meeting the severe resource limits of edge hardware.