Inferensys

Glossary

Flash Attention

An IO-aware exact attention algorithm that minimizes high-bandwidth memory reads and writes by tiling the computation, significantly speeding up transformer models.
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IO-AWARE EXACT ATTENTION

What is Flash Attention?

An algorithm that accelerates the attention mechanism in Transformer models by minimizing reads and writes to high-bandwidth memory through kernel fusion and tiling.

Flash Attention is an IO-aware exact attention algorithm that computes the standard attention operation without approximation while significantly reducing the number of reads and writes to GPU high-bandwidth memory (HBM). By fusing the softmax reduction into a single kernel and tiling the computation to operate entirely within faster SRAM, it avoids materializing the large intermediate attention matrix, which is quadratic in sequence length.

This technique achieves wall-clock speedups of 2-4x and reduces memory consumption from O(N²) to O(N), enabling longer context windows and faster training for large language models. It is a critical optimization in modern self-hosted inference stacks, often integrated into frameworks like vLLM and PyTorch, and is foundational for efficient KV cache management and high-throughput serving.

IO-AWARE EXACT ATTENTION

Key Features of Flash Attention

Flash Attention is an algorithm that computes exact attention with significantly fewer high-bandwidth memory reads and writes by fusing operations and tiling the computation. It delivers wall-clock speedups and memory savings without any approximation.

01

IO-Awareness and Memory Hierarchy

Flash Attention fundamentally restructures the attention computation to be IO-aware, meaning it accounts for the speed disparity between GPU High Bandwidth Memory (HBM) and on-chip Static Random-Access Memory (SRAM). Standard attention materializes the full N×N attention matrix in slow HBM, creating a quadratic memory bottleneck. Flash Attention instead tiles the computation into blocks that fit entirely in fast SRAM, performing the softmax reduction incrementally without ever writing the full intermediate matrix to HBM. This minimizes data movement, the primary bottleneck in transformer inference and training.

7.6x
Memory Read/Write Reduction vs. Standard Attention
02

Tiling and Recomputation Strategy

The algorithm employs a tiling strategy that decomposes the query, key, and value matrices into blocks. For each query block, it iterates over key-value blocks, accumulating softmax statistics in SRAM. Crucially, Flash Attention uses recomputation in the backward pass: rather than storing the massive attention matrix from the forward pass, it recalculates it on-the-fly using the stored softmax normalization statistics. This trades a small amount of extra computation for a dramatic reduction in memory footprint, enabling training with longer sequences on existing hardware.

O(N)
Memory Complexity vs. O(N²) Standard
03

Online Softmax and Numerical Stability

A core mathematical innovation is the online softmax algorithm, also known as tiled softmax. Standard softmax requires two passes over the data: one to find the maximum value for numerical stability and another to compute the exponential sum. Flash Attention fuses these into a single pass per tile by maintaining running statistics. It uses the standard log-sum-exp trick to ensure numerical stability across blocks, rescaling partial sums as new maxima are encountered. This guarantees the output is bitwise identical to the standard attention computation, making it an exact algorithm, not an approximation.

Bitwise Identical
Output Fidelity to Standard Attention
04

Kernel Fusion and CUDA Implementation

Flash Attention is implemented as a single, highly optimized CUDA kernel that fuses multiple operations into one GPU program. Instead of launching separate kernels for matrix multiplication, masking, softmax, and dropout, the entire attention operation is compiled into a monolithic kernel. This eliminates the overhead of launching multiple kernels and, more importantly, avoids the redundant round-trips to HBM that occur between kernel boundaries. The fused kernel carefully manages shared memory allocation and thread block scheduling to maximize occupancy and hide memory latency.

2-4x
Wall-Clock Speedup on GPT-Style Models
06

Impact on Long-Context Training

By reducing the memory footprint of attention from quadratic to linear in sequence length, Flash Attention directly enables training on significantly longer contexts. Models like GPT-4 and Llama 3 rely on this algorithm to scale to context windows of 128k tokens and beyond. Without it, the attention matrix for a 128k sequence would require over 64 GB of memory per attention head, making training infeasible on current hardware. Flash Attention makes long-context training practical on standard GPU clusters, unlocking applications in long-document summarization, codebase analysis, and extended multi-turn conversation.

128k+
Tokens Enabled in Context Windows
FLASH ATTENTION EXPLAINED

Frequently Asked Questions

Clear, technically precise answers to the most common questions about the IO-aware exact attention algorithm that has become fundamental to modern transformer efficiency.

Flash Attention is an IO-aware exact attention algorithm that computes the standard attention mechanism without ever materializing the full N x N attention matrix in high-bandwidth memory (HBM). It works by tiling the query, key, and value matrices into smaller blocks that fit entirely within GPU SRAM, performing the softmax reduction incrementally using an online stable algorithm. By fusing the attention computation into a single CUDA kernel and recomputing the attention matrix during the backward pass rather than storing it, Flash Attention reduces HBM reads and writes from O(N²) to O(N² / M), where M is the SRAM size. This delivers 2-4x wall-clock speedups and reduces memory consumption from quadratic to linear in sequence length, enabling transformers to process much longer contexts without approximation.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.