Inferensys

Glossary

CUDA

CUDA (Compute Unified Device Architecture) is a parallel computing platform and programming model developed by NVIDIA that enables general-purpose computing on its graphics processing units (GPUs), forming the foundational software layer for most AI model training and high-performance computing workloads.
ML engineer managing model training cluster on laptop, GPU utilization visible, technical deep learning setup.
COMPUTE UNIFIED DEVICE ARCHITECTURE

What is CUDA?

The foundational parallel computing platform and programming model that unlocks NVIDIA GPUs for general-purpose processing, forming the software backbone of modern AI.

CUDA is a proprietary parallel computing platform and programming model created by NVIDIA that enables developers to use its graphics processing units (GPUs) for general-purpose computing tasks beyond graphics rendering. By exposing the GPU's massively parallel architecture through standard programming languages like C++ and Python, CUDA allows thousands of threads to execute simultaneously, accelerating computationally intensive workloads such as deep neural network training, scientific simulation, and real-time video processing.

The CUDA software stack comprises a hardware driver, a CUDA Toolkit with compilers and libraries, and the CUDA runtime API. Key libraries like cuBLAS, cuDNN, and NCCL provide highly optimized primitives for linear algebra, deep learning operations, and multi-GPU communication. This vertically integrated ecosystem creates a significant software moat, as the vast majority of AI frameworks—including PyTorch and TensorFlow—rely on CUDA as their primary GPU backend, making it the de facto standard for accelerated computing in enterprise AI infrastructure.

ARCHITECTURAL PRIMITIVES

Key Features of the CUDA Platform

The foundational software abstractions that expose NVIDIA's massively parallel GPU hardware to general-purpose computing, forming the bedrock of modern AI model training and inference.

01

Hierarchical Threading Model

CUDA organizes parallel execution into a grid of thread blocks, each containing hundreds of threads. This two-level hierarchy maps directly to the GPU's Streaming Multiprocessor (SM) architecture. Threads within a block execute concurrently on a single SM and can synchronize via __syncthreads() and share data through ultra-fast shared memory. Blocks within a grid execute independently across multiple SMs, enabling transparent scalability from consumer GPUs to data center clusters without code changes.

Thousands
Threads per SM
~10 cycles
Shared Memory Latency
02

Explicit Memory Hierarchy

CUDA exposes a programmer-managed memory hierarchy to maximize data locality:

  • Global Memory: High-capacity HBM3e, accessible by all threads but with high latency (~hundreds of cycles).
  • L2 Cache: Hardware-managed cache shared across all SMs.
  • Shared Memory: Programmer-managed SRAM within an SM, shared by a thread block.
  • Registers: The fastest memory, private to each thread.
  • Constant/Texture Memory: Read-only caches optimized for specific access patterns. Effective use requires strategic data movement to keep the compute cores saturated.
HBM3e
Global Memory Type
~100x
Shared vs Global BW
03

SIMT Execution Model

CUDA employs a Single Instruction, Multiple Thread (SIMT) architecture. Threads within a block are grouped into warps of 32 threads that execute the same instruction in lockstep on a single SM. Divergent control flow within a warp (e.g., an if-else branch) causes warp divergence, where both paths are serialized, reducing utilization. The CUDA compiler and hardware warp scheduler optimize instruction issue and manage stalls from memory latency by rapidly context-switching between eligible warps.

32
Threads per Warp
Zero-overhead
Warp Scheduling
05

CUDA Streams & Asynchronous Concurrency

A CUDA stream is a sequence of operations (kernel launches, memory copies) that execute in order on the GPU. By creating multiple streams, developers can overlap independent operations to maximize hardware utilization:

  • Overlap data transfers and computation: Copy the next batch of data while the current kernel executes.
  • Concurrent kernel execution: Run multiple small kernels on different SMs simultaneously.
  • CUDA Events provide precise inter-stream synchronization points. This is critical for achieving high throughput in inference serving systems like Triton Inference Server.
Up to 32
Concurrent Kernels
CUDA CLARIFIED

Frequently Asked Questions

Direct answers to the most common technical questions about NVIDIA's parallel computing platform, covering its architecture, compatibility, and operational mechanics.

CUDA (Compute Unified Device Architecture) is a parallel computing platform and programming model developed by NVIDIA that enables general-purpose computing on its proprietary Graphics Processing Units (GPUs). It works by allowing developers to write programs in standard languages like C, C++, and Python, and then offload computationally intensive parallel portions of the code—called kernels—to the GPU. The GPU executes these kernels across thousands of lightweight threads simultaneously, organized into a grid of thread blocks. This Single Instruction, Multiple Thread (SIMT) architecture allows the hardware to mask memory latency by rapidly switching between warps (groups of 32 threads), achieving massive throughput for data-parallel tasks like matrix multiplication, which is foundational to deep learning.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.