Confidential Computing

The CPU automatically encrypts the entire memory space of a protected virtual machine or container. This ensures that even a malicious or compromised host OS, hypervisor, or system administrator with physical access cannot read plaintext data from the processor's memory bus.

• Total Memory Encryption (TME) in Intel and Secure Memory Encryption (SME) in AMD are foundational technologies.
• Encryption keys are generated and managed entirely within the processor package, never exposed to system software.
• Protects against cold-boot attacks, DIMM interposers, and privileged insider threats.

Before any data or code is loaded into a TEE, the platform generates a cryptographically signed attestation report. This report is a verifiable proof of the enclave's identity, firmware versions, and security configuration. A remote relying party can validate this report against the chip manufacturer's certificate chain to establish trust.

• Prevents the injection of code into a fake or tampered enclave.
• Enables a Zero-Trust model where trust is rooted in the silicon vendor, not the infrastructure operator.
• Protocols like Intel's SGX DCAP and AMD's SEV-SNP Attestation standardize this verification.

Traditional virtualization trusts the hypervisor to enforce isolation between guest VMs. A compromised hypervisor breaks all security boundaries. Confidential Computing removes the hypervisor and host OS from the Trusted Compute Base (TCB).

• The processor enforces that memory pages belonging to a TEE are inaccessible to the hypervisor.
• Even a root-level attacker on the host cannot dump the memory of a protected VM.
• This is critical for sovereign AI infrastructure, where the cloud provider's administrators must be treated as potential threat actors.

Confidential Computing is uniquely suited to protect the intellectual property of AI models and the privacy of user prompts during inference. The model weights, user query, and generated response are all encrypted in memory.

• Model Protection: Prevents the cloud operator from stealing proprietary model weights.
• Prompt Privacy: Ensures sensitive user inputs (e.g., medical records, financial data) are never visible to the infrastructure provider.
• Enables confidential multi-party computation where multiple organizations can combine sensitive datasets for training without revealing raw data to each other.

A hardware component integrated into the memory controller that transparently encrypts all data written to DRAM and decrypts data read back. This prevents physical memory bus snooping and cold-boot attacks.

• Total Memory Encryption (TME): AMD's full physical memory encryption with a single ephemeral key
• Multi-Key TME (MKTK): Per-VM encryption keys for isolating multiple tenants
• Intel TME-MK: Multi-key extensions allowing per-enclave memory encryption

Memory encryption operates at line speed with negligible latency overhead, ensuring that even if an attacker physically accesses DIMMs, the data remains cryptographically opaque.

The process of computing a cryptographic hash over the initial code, data, and configuration loaded into a TEE. This measurement uniquely identifies the enclave's trusted computing base (TCB) and is used during attestation.

• MRENCLAVE: In Intel SGX, a SHA-256 hash of the enclave's initial code and data pages
• Launch Measurement: Captures the enclave author's signing identity
• TCB Recovery: Measurements change when firmware or microcode is updated

Any modification to the enclave binary—even a single byte—produces a completely different measurement, making unauthorized code injection immediately detectable during attestation.

A full VM instance where the entire guest memory state is encrypted and isolated from the hypervisor. Unlike process-based enclaves, CVMs require no application modification and support lift-and-shift migration of existing workloads.

• AMD SEV-SNP: Adds integrity protection to prevent hypervisor-based replay attacks
• Intel TDX: Hardware-isolated VMs with a secure arbitration mode for interrupt delivery
• Protected Execution: Guest page tables are managed within the secure processor

CVMs enable organizations to run unmodified databases, ML training, and legacy applications in a confidential computing environment without rearchitecting software.

A dedicated, processor-reserved memory region that stores enclave code and data. The EPC is encrypted by the memory encryption engine and is inaccessible to DMA, the OS, or the hypervisor.

• EPC Size: Typically 64GB to 512GB per socket, limiting enclave memory footprint
• EPC Paging: Swaps encrypted pages to unprotected memory with integrity guarantees
• Cache Coherency: EPC pages participate in the CPU cache hierarchy with encryption at the cache line boundary

EPC capacity is a critical design constraint for confidential workloads—large in-memory databases may require paging optimizations or next-generation processors with expanded EPC.