Side-Channel Resistance

A hardware and OS-level technique that isolates cache lines between security domains to prevent cross-core Prime+Probe or Flush+Reload attacks. By statically partitioning the last-level cache, a malicious process cannot evict or observe the cache lines of a victim enclave.

• Mechanism: Physical page coloring maps virtual addresses to non-overlapping cache sets
• Intel CAT: Cache Allocation Technology enforces per-core cache capacity limits
• ARM MPAM: Memory System Resource Partitioning and Monitoring for Realm isolation
• Benefit: Eliminates contention-based cache side-channels between VMs

Hardware countermeasures that flatten the power profile of cryptographic operations so that the instantaneous current draw reveals no information about the secret key being processed. This defeats Differential Power Analysis (DPA) attacks that sample voltage fluctuations.

• Balanced Logic Styles: Wave Dynamic Differential Logic (WDDL) gates consume equal power for 0→1 and 1→0 transitions
• On-Chip Noise Injection: Random power spikes mask the true signal
• Decoupling Capacitors: Smooth transient current demands to obscure operation boundaries
• Application: Smart card controllers and TEE-bound security co-processors

Microarchitectural defenses that prevent transient execution attacks like Spectre and Meltdown from leaking enclave secrets. These barriers serialize the instruction pipeline at security-critical boundaries, ensuring that speculative loads into protected memory are never visible to side-channel observers.

• LFENCE: Serializes instruction execution, preventing younger loads from completing speculatively
• CSDB: Speculative store bypass barrier on ARM architectures
• Retpoline: A software construct that replaces indirect branches with return trampolines to defeat Branch Target Injection
• FineIBT: Forward-edge control-flow integrity that cryptographically binds branch targets

Physical-layer defenses that attenuate electromagnetic emanations from processors and memory buses to prevent attackers from reconstructing sensitive data via radio-frequency interception. This extends the TCB to include the physical enclosure.

• Faraday Cages: Conductive enclosures that block RF leakage from server chassis
• Differential Signaling: Twisted-pair traces that cancel common-mode EM radiation
• Spread-Spectrum Clocking: Dithers the system clock to smear spectral peaks
• Standard: NATO SDIP-27 defines emission security levels for classified computing

A cryptographic protocol that hides memory access patterns from an untrusted host by continuously shuffling and re-encrypting data blocks. Even if an attacker observes physical memory bus activity, they cannot determine which logical address is being read or written.

• Path ORAM: Stores data in a tree structure, reading and rewriting entire paths on each access
• Circuit ORAM: Optimizes for secure multi-party computation contexts
• Overhead: Typically 20-100x bandwidth overhead vs. unprotected RAM
• Enclave Integration: Used in ZeroTrace to hide page-fault address patterns from the OS

A software implementation discipline where the execution path and memory access patterns are independent of secret data. By eliminating data-dependent branches and variable-cycle instructions, constant-time code prevents attackers from inferring cryptographic keys through timing analysis. This is the primary software defense against timing side-channels in cryptographic libraries like OpenSSL and libsodium.

A class of side-channel attacks that exploit the correlation between a processor's instantaneous power consumption and the data being processed. Simple Power Analysis (SPA) interprets visual traces directly, while Differential Power Analysis (DPA) uses statistical methods to extract secrets from noisy measurements across thousands of operations. Hardware countermeasures include decoupling capacitors and randomized clock generation.

Unintentional radio-frequency signals emitted by processors and memory buses during computation. These emanations can be captured with near-field probes and demodulated to reconstruct screen contents or extract cryptographic keys—a threat known as TEMPEST in defense contexts. Shielding, spread-spectrum clocking, and differential signaling are primary hardware mitigations.

A microarchitectural side-channel where an attacker measures the latency of memory accesses to infer which cache lines were evicted or loaded by a victim process. Spectre and Meltdown are infamous examples. Defenses include cache partitioning (Intel CAT), cache line flushing on context switch, and constant-time algorithms that avoid secret-dependent memory access patterns.

Algorithmic countermeasures that split sensitive intermediate values into multiple random shares using secret-sharing schemes. The computation is performed on each share independently, and the correct result is reconstructed at the end. Because each share is statistically independent of the secret, power and EM leakage becomes uncorrelated. Blinding applies similar randomization to cryptographic operations like RSA decryption.

Physical countermeasures integrated into secure processors that inject random electrical noise or execute dummy operations to obscure the true power signature. Modern secure elements and TEE-capable CPUs use dedicated noise engines and randomized instruction scheduling to flatten the power profile, making statistical correlation attacks exponentially more difficult.