Hardware-in-the-Loop (HIL)

HIL simulation creates a closed-loop system where the simulated grid responds instantaneously to the actions of the physical device under test. The digital real-time simulator (DRTS) solves power system equations in sub-microsecond time steps, outputting low-level analog voltage and current signals that mirror what a relay or PMU would see in the field. The physical device processes these signals, makes a decision (e.g., issuing a trip command), and that decision is fed back into the simulation, altering the grid model's state in the next time step. This bidirectional, deterministic interaction is the defining characteristic that distinguishes HIL from simple playback testing.

The interface between the simulator and the physical hardware operates at the signal level, not the data protocol level. The DRTS uses high-precision digital-to-analog converters (DACs) and voltage/current amplifiers to replicate the secondary signals from instrument transformers (CTs and VTs) at their native low-energy levels (±10V or ±1A). This tests the device's entire acquisition chain—its analog filtering, analog-to-digital conversion, and internal algorithms—exposing vulnerabilities that a simple IEC 61850 Sampled Values injection would miss. For PMU testing, this validates the accuracy of the device's Total Vector Error (TVE) under dynamic conditions as defined by IEEE C37.118.

HIL enables the safe, repeatable execution of destructive test scenarios that are impossible or prohibitively dangerous to stage on a live grid. Engineers can inject a near-infinite variety of fault types at any point on the virtual network:

• Evolving faults: A single-phase-to-ground fault that escalates into a three-phase fault.
• CT saturation: Simulating the non-linear behavior of a saturated current transformer during a high-magnitude close-in fault.
• Power swing conditions: Testing whether a distance relay correctly distinguishes a stable power swing from an actual fault.
• Subsynchronous oscillations: Injecting SSO frequencies to validate generator protection and torsional stress relays.

HIL testbeds are scriptable, enabling fully automated regression testing against industry standards. A test script can programmatically execute every test waveform defined in a protection standard (e.g., IEEE C37.118.1 for PMUs or IEC 60255 for protection relays), log the device's response, and generate a pass/fail compliance report without human intervention. This is critical for:

• Firmware validation: Ensuring a new relay firmware version does not introduce a regression in protection element timing.
• Type testing: Certifying that a new PMU model meets the dynamic compliance requirements for M-class or P-class performance before utility acceptance.

Beyond single-device testing, HIL platforms can be geographically distributed and interconnected to form a virtual wide-area grid. Multiple physical PMUs, relays, and Phasor Data Concentrators (PDCs) at different locations can be connected to a single, coherent real-time simulation. This validates the entire WAMPAC chain: the PMU measures the simulated oscillation, the PDC time-aligns the data, the wide-area controller processes it, and a corrective command is sent back to a physical SVC or HVDC controller in another HIL lab. This end-to-end testing validates communication latency, data alignment integrity, and the closed-loop stability of System Integrity Protection Schemes (SIPS) before field commissioning.

HIL occupies a specific position in a spectrum of simulation fidelity:

• Software-in-the-Loop (SIL): The control algorithm and the plant model are both pure software. No real-time constraint. Used for early algorithm development.
• Controller-Hardware-in-the-Loop (CHIL): The physical controller (relay, PMU) is connected to a simulated power system via low-level analog/digital signals. This is the classic HIL definition.
• Power-Hardware-in-the-Loop (PHIL): A physical power device (e.g., a 50 kW solar inverter) exchanges real power with a simulated grid via a power amplifier and a physical bus. This tests the device's actual power electronics, thermal behavior, and grid-forming capability, requiring a much more complex and higher-power interface than CHIL.

The computational core of a HIL setup. A DRTS solves complex power system equations in real-time with time steps typically between 1-50 microseconds. Unlike offline simulation, it must guarantee deterministic execution to interact with physical hardware without timing errors.

• Key Vendors: RTDS Technologies, OPAL-RT, Typhoon HIL
• Critical Spec: Hard real-time constraint; missing a single time step invalidates the test
• Architecture: Often uses FPGAs for ultra-low-latency I/O and parallel processing

The interface layer that bridges the low-voltage output of a DRTS to the high-voltage inputs expected by physical protection relays and PMUs. Current amplifiers and voltage amplifiers scale simulated signals to nominal secondary levels (e.g., 1A/5A current, 110V voltage) with high fidelity.

• Total Harmonic Distortion (THD): Must be < 0.1% to avoid introducing artificial errors
• Bandwidth: Typically DC to 10 kHz to capture transient phenomena
• Galvanic Isolation: Critical to protect sensitive digital simulation hardware from physical device faults

Modern HIL testing for digital substations requires the DRTS to communicate natively using IEC 61850 protocols. The simulator must publish GOOSE (Generic Object Oriented Substation Event) messages to trip relays and subscribe to Sampled Values (SV) streams to close the loop with merging units.

• GOOSE: High-speed peer-to-peer messaging for protection signaling (< 3 ms latency)
• Sampled Values: Streams of digitized CT/VT measurements at 80 samples/cycle (4 kHz)
• Test Scenario: Inject a fault SV stream and verify the relay issues a GOOSE trip within a specified time window

An advanced extension of signal-level HIL where actual power flows are exchanged between the simulation and physical hardware. A power amplifier and interface algorithm absorb or inject real current, allowing testing of physical inverters, EV chargers, or microgrid controllers at rated power.

• Stability Challenge: The interface algorithm must prevent instability caused by time delay and impedance mismatch at the boundary
• Ideal Transformer Method (ITM): A common interface algorithm, but prone to instability if the simulated impedance is much larger than the physical impedance
• Damping Impedance Method (DIM): Adds a virtual impedance to stabilize the interface, sacrificing some accuracy for robust operation

HIL testing is integrated into CI/CD pipelines for protection firmware. Automated scripts execute thousands of fault scenarios—varying fault type, location, inception angle, and system topology—to validate relay behavior against IEEE C37.118 or manufacturer specifications.

• Tools: Python scripting with DRTS APIs, TestStand, or custom frameworks
• Output: Pass/fail reports with Total Vector Error (TVE) and timing accuracy metrics
• Regression Testing: Ensures a new firmware version does not break previously validated protection schemes

For HIL testing of PMUs and synchrophasor applications, the DRTS must simulate a GPS-disciplined time source. The simulator generates an IRIG-B or PTP (IEEE 1588) signal to synchronize the physical PMU under test, allowing validation of timestamp accuracy and time-error tolerance.

• Test Scenario: Simulate a GPS holdover event and verify the PMU flags data as unreliable
• Metric: Time error must be measured against a traceable reference to validate PMU compliance with IEEE C37.118.1