TinyML Disaggregation

Reduces the numerical precision of neural network weights from 32-bit floating-point to 8-bit integers (INT8). This shrinks model size by 4x and enables integer arithmetic on microcontrollers without floating-point units.

• Post-training quantization calibrates activation ranges using representative data
• Quantization-aware training simulates low-precision effects during optimization
• Minimal accuracy loss (often <1%) while achieving sub-100KB model footprints

Executes the disaggregation algorithm directly on the smart meter or embedded sensor rather than streaming high-frequency data to the cloud. This eliminates latency, preserves privacy, and enables operation in disconnected environments.

• Inference latency typically under 10 milliseconds per prediction window
• Eliminates bandwidth costs associated with transmitting kilohertz-rate electrical data
• Enables real-time appliance-level feedback directly to consumers

Employs neural network designs specifically engineered for microcontroller-class hardware with as little as 256KB of RAM and 1MB of flash storage. These architectures strip away unnecessary parameters while preserving disaggregation accuracy.

• Depthwise separable convolutions reduce parameter count by 8-9x versus standard convolutions
• Pruning removes redundant connections, yielding sparse models with 50-90% fewer weights
• Knowledge distillation transfers expertise from large teacher models to compact student networks

Orchestrates disaggregation inference to minimize the energy budget of the sensing device itself. This is critical for battery-powered or energy-harvesting sensors that must operate for years without maintenance.

• Duty cycling activates inference only when significant aggregate power changes are detected
• Event-driven wake-up circuits trigger the MCU from deep sleep on transient current spikes
• Inference batching processes multiple windows in a single wake cycle to amortize startup costs

Combines aggregate electrical measurements with auxiliary low-power sensor inputs to improve disaggregation accuracy without violating resource constraints. Contextual awareness helps disambiguate appliances with similar electrical signatures.

• Passive infrared (PIR) sensors detect room occupancy to correlate with appliance state changes
• Ambient light sensors distinguish daytime appliance usage patterns from nighttime baselines
• Time-of-day and day-of-week features encoded as compact cyclical embeddings

The process of reducing the numerical precision of a neural network's weights and activations from 32-bit floating-point to 8-bit integers. This drastically shrinks model size and accelerates inference on microcontrollers.

• Post-Training Quantization (PTQ): Applied after training, often with minimal accuracy loss.
• Quantization-Aware Training (QAT): Simulates quantization during training for higher final accuracy.
• Memory Reduction: An 8-bit model is roughly 4x smaller than its 32-bit equivalent.

A compression technique where a compact student model is trained to mimic the output distribution of a larger, high-accuracy teacher model. The student learns to replicate the teacher's generalization without memorizing its full parameter count.

• Soft Targets: The student learns from the teacher's probability outputs, capturing subtle class relationships.
• Application: A complex deep NILM model can be distilled into a lightweight network suitable for an ARM Cortex-M processor.

An open-source inference framework designed to run machine learning models on bare-metal or RTOS-based microcontrollers with only kilobytes of memory. It interprets flatbuffer model files and executes operators with minimal overhead.

• Footprint: Core runtime fits in 16 KB of flash on Arm Cortex-M3+.
• Operator Support: Includes a curated subset of ops optimized for integer-only execution.
• No OS Required: Can run directly on the metal without a standard operating system.

A complete development lifecycle platform for embedded ML, from data ingestion to deployment. It automates signal processing, neural architecture search, and generates optimized C++ libraries for specific MCU targets.

• DSP Block: Automatically extracts features like RMS and FFT from raw electrical signals.
• EON Tuner: Simultaneously searches for optimal model architecture and signal processing parameters.
• Targets: Supports deployment to Arduino, STM32, and EFR32 series microcontrollers.

The computation of discriminative electrical characteristics directly on the sensor node before inference. This reduces the dimensionality of raw data and minimizes the workload on the neural network.

• RMS Current & Voltage: Fundamental steady-state metrics computed via sliding window.
• FFT Harmonics: Spectral analysis to identify unique frequency-domain signatures of appliances.
• Active/Reactive Power: Calculated from instantaneous voltage and current samples to capture phase shifts.

Power management strategies that keep the microcontroller in deep sleep mode for the majority of the time. A low-power comparator or RTC alarm wakes the system only when a significant power event is detected.

• Threshold Wake-Up: An analog front-end triggers an interrupt when aggregate current exceeds a set point.
• Inference Cadence: The MCU wakes, samples a short buffer, runs inference, and returns to sleep in under 100 ms.
• Energy Budget: Enables multi-year operation on a single coin-cell battery.