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Glossary

CUDA

CUDA (Compute Unified Device Architecture) is NVIDIA's parallel computing platform and API model that enables general-purpose processing on GPUs for accelerated computing.
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PARALLEL COMPUTING PLATFORM

What is CUDA?

CUDA is the foundational parallel computing platform and programming model developed by NVIDIA for general-purpose processing on its GPUs.

CUDA (Compute Unified Device Architecture) is a parallel computing platform and application programming interface (API) model created by NVIDIA that enables software developers to use a CUDA-enabled graphics processing unit (GPU) for general purpose processing—an approach known as GPGPU (General-Purpose computing on GPUs). It provides a software layer that abstracts the GPU's massively parallel architecture, allowing developers to write programs in languages like C, C++, and Fortran that execute thousands of concurrent threads to accelerate computationally intensive workloads.

The core of CUDA programming involves writing kernels—functions that execute in parallel across many GPU threads—and managing data transfer between the host (CPU) and device (GPU) memory. This model is essential for high-performance computing (HPC), deep learning training and inference, and parallelized simulation infrastructure, where tasks like matrix operations and physics calculations can be dramatically accelerated. CUDA works in conjunction with specialized libraries like cuDNN and cuBLAS and forms the hardware-software foundation for AI frameworks such as TensorFlow and PyTorch.

ARCHITECTURE

Core Components of the CUDA Platform

CUDA is a parallel computing platform and API model created by NVIDIA that enables general-purpose processing on GPUs. Its architecture is built around several key abstractions that allow developers to harness massive parallelism.

01

CUDA Thread Hierarchy

The execution model is organized into a hierarchical grid of threads. A kernel is launched as a grid of thread blocks. Each block contains many threads, which execute the kernel code in parallel.

  • Thread: The smallest execution unit.
  • Thread Block: A group of threads that can cooperate via shared memory and synchronize.
  • Grid: A collection of thread blocks that execute a kernel.

This hierarchy maps directly to GPU hardware: threads run on CUDA Cores, blocks are scheduled on Streaming Multiprocessors (SMs), and the grid fills the entire GPU.

02

CUDA Memory Model

CUDA exposes a tiered memory architecture, each with distinct performance characteristics and scope.

  • Global Memory: High-latency, large-capacity memory visible to all threads. The primary means for host (CPU) and device (GPU) communication.
  • Shared Memory: Extremely fast, programmer-managed memory shared by threads within a block. Crucial for optimizing data reuse.
  • Registers: The fastest memory, private to each thread. Used for thread-local variables.
  • Constant Memory: Cached, read-only memory for data that is constant for the lifetime of a kernel.
  • Texture Memory: Optimized for 2D spatial locality with cached, read-only access.

Efficient algorithms carefully stage data from global to shared memory to minimize latency.

03

Streaming Multiprocessor (SM)

The Streaming Multiprocessor (SM) is the fundamental processing unit inside an NVIDIA GPU. Each SM contains:

  • CUDA Cores: Scalar processors for integer and single-precision floating-point arithmetic.
  • Tensor Cores: Dedicated units for mixed-precision matrix operations, accelerating deep learning (from Volta architecture onward).
  • RT Cores: Dedicated hardware for ray tracing acceleration (from Turing architecture onward).
  • Warp Schedulers: Manage the execution of warps (groups of 32 threads, the fundamental unit of execution).
  • Shared Memory / L1 Cache: A configurable on-chip memory pool.

A GPU contains many SMs, enabling massive data parallelism. Thread blocks are distributed across available SMs for execution.

04

CUDA Runtime & Driver API

CUDA provides two layers of APIs for programming.

  • CUDA Runtime API (cudart): A higher-level, convenience API. Functions like cudaMalloc() and cudaMemcpy() are part of this layer. It handles implicit initialization, context management, and module loading. Most applications use this API.
  • CUDA Driver API: A lower-level, more control-oriented API. It provides finer-grained management over contexts, modules, and kernel execution. It is more verbose but offers capabilities like managing multiple GPUs with more control. The Runtime API is built on top of the Driver API.

Both APIs are accessible from C, C++, and through bindings in languages like Python and Fortran.

05

CUDA Compilation (NVCC)

NVCC is the NVIDIA CUDA compiler driver. It separates code meant for the GPU (device code) from code meant for the CPU (host code).

  • Device code (marked with __global__ or __device__ keywords) is compiled to PTX (Parallel Thread Execution), a low-level virtual machine assembly language, and then to SASS (native GPU machine code).
  • Host code is compiled by the system's native C++ compiler (e.g., g++, cl).
  • NVCC orchestrates this split compilation, linking the host and device code into a single executable or library.
  • Just-In-Time (JIT) Compilation: At runtime, a driver can compile PTX code to the target GPU's native SASS, ensuring forward compatibility.
PARALLEL COMPUTING

CUDA Programming Model and Execution Hierarchy

The CUDA programming model is a parallel computing architecture that enables developers to write software that executes on NVIDIA GPUs, organizing computations into a hierarchical structure of threads, blocks, and grids for massive parallelism.

The CUDA programming model is a software abstraction that exposes the massively parallel architecture of NVIDIA Graphics Processing Units (GPUs) for general-purpose computing. It extends languages like C++ with keywords and APIs, allowing developers to write functions called kernels that are executed in parallel by thousands of lightweight threads. The model's execution hierarchy organizes these threads into thread blocks and grids of blocks, mapping logically to the GPU's physical streaming multiprocessors. This structure is fundamental for leveraging the Single Instruction, Multiple Thread (SIMT) execution paradigm, where many threads run the same instruction on different data simultaneously.

The execution hierarchy defines how a kernel's workload is partitioned. A grid represents the entire kernel launch, composed of multiple thread blocks. Each block contains a collection of threads that can cooperate via fast shared memory and synchronization. This hierarchy allows the hardware scheduler to distribute blocks across the GPU's Streaming Multiprocessors (SMs). For optimal performance, developers must carefully design this hierarchy to maximize occupancy—the number of active warps (groups of 32 threads) per SM—and ensure efficient memory access patterns across the GPU's memory hierarchy, which includes registers, shared memory, and global memory.

CUDA

Primary Use Cases and Applications

CUDA's parallel computing model is foundational for accelerating workloads where massive data parallelism can be exploited. Its primary applications span scientific computing, artificial intelligence, and high-fidelity simulation.

COMPARISON

CUDA vs. Alternative GPU Computing Platforms

A technical comparison of NVIDIA's CUDA platform against major alternatives for general-purpose GPU computing, focusing on features relevant to parallelized simulation and high-performance computing.

Feature / MetricNVIDIA CUDAAMD ROCmOpenCL / SYCLApple Metal

Primary Vendor / Consortium

NVIDIA

AMD

Khronos Group / Intel

Apple

Programming Model

Single-source (C/C++/Fortran/Python extensions)

Heterogeneous-compute Interface for Portability (HIP), Single-source

Multi-source (host/device code separation), Explicit offload

Single-source (Metal Shading Language, Swift/C++)

Hardware Ecosystem Breadth

NVIDIA GPUs only

AMD Instinct & Radeon GPUs, limited support on some CPUs

Cross-vendor (CPUs, GPUs, FPGAs from NVIDIA, AMD, Intel, others)

Apple Silicon (M-series) GPUs only

Kernel Launch Latency

< 5 µs

~10-20 µs

50 µs (OpenCL), ~10 µs (SYCL via oneAPI)

< 10 µs

Peer-to-Peer GPU Direct Access

✅ (NVLink, GPUDirect)

✅ (AMD XGMI for Instinct)

❌ (Managed by host/driver)

✅ (On-chip unified memory)

Multi-GPU & Multi-Node Communication Library

NCCL (optimized for NVIDIA)

RCCL (ROCm Communication Collectives Library)

No standardized, vendor-optimized library

Metal Performance Shaders (MPS) Graph (single node)

Profiling & Debugging Tools

Nsight Systems, Nsight Compute (comprehensive)

ROCProfiler, ROCgdb (functional, less mature)

Limited vendor-specific tools (Intel VTune, CodeXL)

Instruments, Metal System Trace (Apple-centric)

Container & Cloud Native Support

✅ (NVIDIA Container Toolkit, cloud VM images)

✅ (ROCm containers, limited cloud availability)

Varies by vendor/implementation

❌ (Tightly integrated with macOS/iOS)

Key Use Case in Parallel Simulation

Massively parallel physics stepping, RL policy training

Alternative for large-batch HPC workloads

Portable code for diverse hardware testbeds

On-device inference & lightweight simulation on Mac

Memory Management Model

Explicit (cudaMalloc/cudaFree) & Unified Memory (optional)

Explicit (hipMalloc) & HIP Managed Memory

Explicit buffer-based (OpenCL), USM (SYCL)

Implicit (Unified Memory by default)

Interoperability with Graphics APIs

✅ (DirectX, Vulkan, OpenGL via CUDA interop)

✅ (Vulkan, DirectX 12)

✅ (Often used for compute-only contexts)

✅ (Tightly integrated with Metal graphics)

Approximate Peak FP32 TFLOP/s (Example GPU)

~100 TFLOP/s (NVIDIA H100)

~48 TFLOP/s (AMD MI250X)

Varies widely by hardware

~5.8 TFLOP/s (Apple M3 Max)

Community & Library Ecosystem

Extensive (cuDNN, cuBLAS, cuSOLVER, PhysX, Omniverse)

Growing (MIOpen, rocBLAS, rocSOLVER)

Broad but fragmented (vendor-specific optimizations vary)

Niche, Apple-focused (Core ML, ML Compute)

CUDA

Frequently Asked Questions

CUDA (Compute Unified Device Architecture) is NVIDIA's parallel computing platform and API model that enables general-purpose processing on GPUs. This FAQ addresses its core concepts, applications, and role in modern AI infrastructure.

CUDA (Compute Unified Device Architecture) is a parallel computing platform and application programming interface (API) model created by NVIDIA that enables software developers to use CUDA-enabled Graphics Processing Units (GPUs) for general-purpose processing, a paradigm known as GPGPU (General-Purpose computing on GPUs). It works by extending programming languages like C, C++, and Fortran, allowing developers to write functions called kernels that are executed N times in parallel by N different CUDA threads. The architecture exposes the GPU's massively parallel streaming multiprocessors (SMs) as a scalable data-parallel computing device, managed through a hierarchy of threads, blocks, and grids. The host CPU launches kernels, which are then offloaded to the GPU, where thousands of threads execute the same instruction on different data elements simultaneously, providing immense throughput for parallelizable workloads.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.