Inferensys

Glossary

FlashAttention

An exact-attention algorithm that minimizes high-bandwidth memory reads and writes between GPU HBM and SRAM by fusing operations in a tiled, IO-aware manner, significantly accelerating training and inference.
ML engineer managing model training cluster on laptop, GPU utilization visible, technical deep learning setup.
IO-AWARE EXACT ATTENTION

What is FlashAttention?

FlashAttention is an algorithm that computes exact self-attention with significantly reduced memory reads and writes by fusing operations in a tiled, IO-aware manner.

FlashAttention is an exact-attention algorithm that minimizes high-bandwidth memory (HBM) reads and writes between GPU HBM and on-chip SRAM. It achieves this by fusing operations in a tiled, IO-aware manner, dramatically accelerating both training and inference of Transformer models without any approximation of the attention mechanism.

By restructuring the computation to keep intermediate matrices in fast SRAM, FlashAttention reduces the memory footprint from quadratic to linear in sequence length. This enables training on longer context windows and delivers significant wall-clock speedups, making it a foundational optimization in modern large language model implementations.

IO-AWARE EXACT ATTENTION

Key Features of FlashAttention

FlashAttention is an algorithm that accelerates the exact attention computation by minimizing slow, high-bandwidth memory (HBM) reads and writes. It achieves this by fusing operations in a tiled, IO-aware manner, keeping data in fast on-chip SRAM.

01

IO-Awareness: Tiling for SRAM

The core innovation is tiling the attention computation to fit into the limited, high-bandwidth GPU SRAM. Instead of materializing the full N x N attention matrix in slow HBM, FlashAttention loads blocks of Query (Q), Key (K), and Value (V) matrices from HBM to SRAM, computes attention on the block, and writes only the final output back. This drastically reduces HBM read/write operations, the primary bottleneck in standard attention.

02

Exact Attention with No Approximation

Unlike sparse attention or low-rank approximation methods, FlashAttention computes mathematically identical results to standard attention. It uses a numerically stable online softmax algorithm, known as tiled softmax or online normalizer calculation, to correctly rescale block statistics without needing the full row of attention scores. This guarantees no loss in model quality while achieving significant speedups.

03

Recomputation Over Storage for Backward Pass

To remain memory-efficient during training, FlashAttention avoids storing the large intermediate attention matrix for the backward pass. Instead, it recomputes the attention scores and softmax statistics during the backward pass by reloading the Q, K, V blocks from HBM. This recomputation strategy trades extra FLOPs for a massive reduction in memory footprint, enabling training with longer sequences.

04

Algorithmic Fusion of Operations

FlashAttention implements kernel fusion by combining multiple CUDA kernels into a single, highly optimized kernel. Operations like the matrix multiply, softmax scaling, dropout masking, and the final output accumulation are all performed in a single pass over the data while it resides in SRAM. This eliminates the overhead of launching multiple kernels and the associated round-trips to HBM.

05

Massive Memory Footprint Reduction

Standard attention has a memory complexity of O(N²) with sequence length N, which quickly exhausts GPU HBM for long sequences. FlashAttention reduces the memory footprint to O(N) by never materializing the full attention matrix. This allows training Transformers on sequence lengths of 8k, 16k, or even 64k tokens, which was previously infeasible without model parallelism or approximation.

06

Wall-Clock Speedup for Training and Inference

By shifting the bottleneck from memory bandwidth to compute speed, FlashAttention delivers 2-4x wall-clock speedups for the attention layer. This translates to significant end-to-end training time reductions for models like GPT and BERT. For inference, FlashAttention accelerates the prefill phase and, in its FlashDecoding variant, optimizes the generation phase by parallelizing the attention computation across the sequence length dimension.

ATTENTION MECHANISM COMPARISON

FlashAttention vs. Standard Attention vs. Sparse Attention

A technical comparison of exact, IO-aware attention against standard exact attention and approximate sparse attention methods, focusing on memory access patterns, computational complexity, and implementation characteristics.

FeatureFlashAttentionStandard AttentionSparse Attention

Exact Attention Computation

IO-Aware Tiling Strategy

Memory Complexity (Sequence Length n)

O(n)

O(n²)

O(n) to O(n√n)

Primary Memory Working Set

GPU SRAM (on-chip)

GPU HBM (off-chip)

GPU HBM (off-chip)

HBM Read/Write Operations

Minimal (fused kernel)

High (materializes full matrix)

Reduced (partial matrix)

Backward Pass Recomputation

Attention Pattern

Full (exact, tiled)

Full (exact, dense)

Predefined mask (local, strided, global)

Training Speedup vs. Standard (GPT-2 scale)

2-4x

1x (baseline)

1.5-3x

FLASHATTENTION FAQ

Frequently Asked Questions

Clear answers to common questions about the IO-aware exact attention algorithm that is accelerating large language model training and inference.

FlashAttention is an exact-attention algorithm that computes the standard self-attention operation without approximation, but with significantly faster wall-clock speed and lower memory usage. It works by minimizing high-bandwidth memory (HBM) reads and writes between GPU DRAM and on-chip SRAM. Instead of materializing the full quadratic N x N attention score matrix in slow HBM, FlashAttention uses tiling to load blocks of the Query, Key, and Value matrices into fast SRAM, computes the softmax attention on-chip block-by-block, and writes only the final output back to HBM. This IO-aware design is implemented in custom CUDA kernels that fuse the entire attention operation—matrix multiply, softmax, and weighted sum—into a single kernel, eliminating redundant memory transfers. The algorithm achieves up to 7.6x speedup on long sequences while using memory linear in sequence length, enabling training of models with 8K+ context windows without model parallelism.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.