Software-Defined Radio

Modern SDRs digitize signals directly at the antenna, eliminating analog down-conversion stages. This provides the raw IQ sample streams that RFML models require for end-to-end learning.

• Instantaneous bandwidth exceeding 100 MHz on platforms like the Ettus X440
• Preserves phase coherence critical for neural beamforming and angle-of-arrival estimation
• Enables direct capture of wideband signals like 5G NR carriers without channelization

Onboard FPGAs execute high-throughput signal processing with deterministic latency, enabling closed-loop RFML inference at the physical layer.

• Implements custom neural network accelerators directly in programmable logic
• Performs digital down-conversion, filtering, and decimation before host transfer
• Supports hardware-in-the-loop testing with sub-millisecond reaction times for cognitive radio applications

Ecosystems like GNU Radio and UHD provide complete software stacks for rapid RFML prototyping without vendor lock-in.

• gr-ml and gr-dnn out-of-tree modules integrate TensorFlow and PyTorch directly into flowgraphs
• Python and C++ APIs allow seamless integration with ML training pipelines
• Community-maintained blocks for modulation classification, spectrum sensing, and channel estimation accelerate research

SDRs with shared local oscillators and synchronized clocks enable coherent multi-antenna operation essential for spatial signal processing and MIMO research.

• Phase-aligned receive chains for angle of arrival and beamforming experiments
• Supports up to 8×8 MIMO configurations on platforms like the USRP N321
• Enables over-the-air collection of spatial covariance matrices for deep learning-based channel estimation

A single SDR platform can cover from near-DC to millimeter-wave frequencies, enabling cross-band RFML research on a unified hardware platform.

• Coverage from 1 MHz to 7.2 GHz on common platforms, with up/downconverters extending to mmWave
• Allows training models on diverse signal types: HF, VHF, UHF, cellular, WiFi, and satellite bands
• Critical for domain generalization research where models must operate across disparate spectral environments

Hardware-level timestamping with GPS-disciplined oscillators provides nanosecond-accurate time alignment across distributed SDR nodes.

• Enables TDOA and TDOA-based geolocation datasets for supervised learning
• Supports synchronous spectrum capture across geographically separated sensors
• Critical for federated learning experiments requiring temporally aligned RF observations from multiple edge nodes

The analog hardware chain that interfaces between the antenna and the digital backend. It performs critical signal conditioning including low-noise amplification (LNA), filtering to reject out-of-band interference, and frequency downconversion from RF to an intermediate frequency (IF) or baseband. The front-end's noise figure and linearity fundamentally constrain the dynamic range of the entire SDR system.

The ADC bridges the analog and digital domains by sampling the conditioned RF waveform at a rate determined by the Nyquist-Shannon sampling theorem. Key specifications include:

• Sample Rate: Must exceed twice the signal bandwidth for alias-free capture
• Effective Number of Bits (ENOB) : Quantifies real-world dynamic range after accounting for noise and distortion
• SFDR: Spurious-Free Dynamic Range, measuring the converter's ability to detect weak signals in the presence of strong interferers

A digital signal processing block that performs frequency translation, decimation, and matched filtering entirely in the digital domain. The DDC mixes the digitized signal with a numerically controlled oscillator (NCO) to shift the desired channel to baseband, then applies cascaded integrator-comb (CIC) and finite impulse response (FIR) filters to reduce the sample rate while preserving the signal of interest.

A Field-Programmable Gate Array provides hardware-level parallelism for high-throughput, low-latency signal processing tasks that would overwhelm a general-purpose CPU. FPGAs excel at:

• Real-time channelization of wideband spectrum into hundreds of narrowband sub-channels
• Packet detection and time synchronization at microsecond granularity
• Custom hardware accelerators for neural network inference directly on IQ samples

An open-source software toolkit that provides a block-based signal processing architecture for building SDR applications. Users construct flowgraphs by connecting processing blocks—sources, sinks, modulators, filters—in a graphical environment or via Python. GNU Radio's extensive library of pre-built blocks accelerates prototyping of cognitive radio and spectrum sensing algorithms without requiring FPGA expertise.

The complex baseband format used throughout SDR processing chains, where signals are represented as In-phase (I) and Quadrature (Q) components. This representation preserves both amplitude and phase information, enabling coherent demodulation and vector signal analysis. IQ imbalance—gain or phase mismatch between the I and Q paths—is a critical hardware impairment that must be calibrated out for accurate modulation classification.