Analog In-Memory Computing (AIMC)

AIMC eliminates the von Neumann bottleneck by co-locating compute and memory. Input voltages (vector) are applied to rows of a resistive memory crossbar. The current output at each column is the dot product of the input vector and the conductance matrix, computed instantaneously via Ohm's law (I=VG) and Kirchhoff's current law.

• Key Benefit: O(1) time complexity for MVM operations, independent of matrix dimensions.
• Mechanism: Weights are stored as analog conductance values in non-volatile memory elements like Phase-Change Memory (PCM) or Resistive RAM (ReRAM).

AIMC cores store synaptic weights directly in non-volatile memory devices, eliminating the energy cost of shuttling data between off-chip DRAM and a CPU/GPU. Devices like PCM and ReRAM retain their programmed conductance state without power, enabling instant-on inference.

• PCM: Stores weights via amorphous/crystalline phase transitions, offering high dynamic range.
• ReRAM: Stores weights via filamentary resistive switching, offering high endurance.
• Critical Challenge: These devices suffer from intrinsic conductance drift and programming variability.

Standard quantization-aware training (QAT) is insufficient for AIMC. Models must be hardened against analog-specific noise sources including programming inaccuracies, read noise, and temporal conductance drift. Hardware-aware training injects statistical models of these non-idealities directly into the forward pass.

• Drift Compensation: Training with simulated conductance decay over time.
• Stochastic Rounding: Mimicking the probabilistic nature of programming analog devices.
• Goal: Ensure inference accuracy remains stable over the chip's lifetime without frequent recalibration.

Conductance drift in PCM devices causes a temporal increase in resistance, degrading weight precision and model accuracy. Mitigation requires a multi-layered approach combining algorithmic and hardware strategies.

• Global Drift Compensation (GDC): Applies a single time-dependent correction factor to all weights based on a calibrated drift model.
• Statistical Weight Mapping: Distributes a single logical weight across multiple physical devices to average out individual drift trajectories.
• Drift-Regularized Training: Penalizes the model during training for relying on weight states highly susceptible to drift.

AIMC achieves orders-of-magnitude improvement in energy efficiency for inference workloads compared to digital accelerators. By performing computation in the analog domain, it avoids the energy-intensive data movement and digital multiply-accumulate operations of traditional architectures.

• Metric: Measured in TOPS/Watt (Tera Operations Per Second per Watt).
• Advantage: Ideal for power-constrained edge devices performing complex RF signal processing tasks like channel estimation.
• Trade-off: This extreme efficiency comes at the cost of reduced numerical precision (typically 4-bit equivalent or less).

Due to chip-to-chip variations in analog device characteristics, a one-size-fits-all model is suboptimal. Chip-in-the-loop optimization fine-tunes a pre-trained model's weights on the specific physical chip instance it will be deployed on.

• Process: A closed-loop system iteratively programs weights, measures the resulting MVM error, and adjusts the digital weight representation to compensate for the physical array's unique imperfections.
• Outcome: Maximizes inference accuracy on the target silicon by learning its specific non-ideality fingerprint.

A non-volatile memory technology that stores data by switching a chalcogenide glass material between amorphous (high resistance) and crystalline (low resistance) states using thermal pulses. In AIMC, PCM cells act as programmable resistors in a crossbar array, encoding weight values as conductance levels. The key challenge is resistance drift—the amorphous phase structurally relaxes over time, causing conductance to decay and degrading matrix-vector multiplication accuracy without periodic compensation.

The fundamental physical principle enabling AIMC. In a crossbar array, Ohm's Law dictates that current through each cell equals voltage multiplied by conductance (I = V × G). Kirchhoff's Current Law sums these currents along each column. When an input vector is applied as voltages to the rows, the total current on each column instantaneously represents the dot product of the input vector and the conductance vector stored in that column. This performs an analog matrix-vector multiplication in a single, constant-time step, independent of matrix dimensions.

The peripheral circuit that quantizes the accumulated analog current on each column into a digital value for downstream processing. ADCs dominate the energy and area budget of an AIMC tile. The design tension is between:

• Resolution: Higher bits reduce quantization noise but increase energy per conversion exponentially.
• Throughput: Faster sampling rates are needed for high-speed inference.
• Area: One ADC per column is ideal for parallelism but prohibitive; column-sharing architectures introduce serialization latency.

A technique to represent both positive and negative weight values using pairs of memory cells that only store positive conductance. A weight W is encoded as the difference between two conductances: W = G⁺ - G⁻. During computation, the input voltage is applied to both cells, and the resulting currents are subtracted. This doubles the array size and ADC count but eliminates the need for signed conductance devices. It also provides first-order cancellation of common-mode noise and drift effects, improving signal integrity.

Non-idealities in the metal interconnect of the crossbar that distort the ideal matrix-vector multiplication. IR drop refers to voltage degradation along power supply lines due to wire resistance, causing cells farther from the source to receive a lower effective input voltage. Parasitic capacitance and inductance introduce RC delays and signal coupling. These effects are particularly severe in large arrays and must be modeled during Hardware-in-the-Loop Optimization or compensated through peripheral circuit calibration.