Costas Loop

Unlike standard PLLs that lock onto a discrete carrier tone, the Costas Loop recovers the carrier from a suppressed-carrier signal where the carrier is absent from the transmitted spectrum. It does this by using the modulation itself to generate a phase error signal. The loop effectively squares or multiplies the incoming signal to create a discrete frequency component at the carrier frequency, which the PLL can then lock onto. This is essential for demodulating BPSK and QPSK signals, where transmitting a carrier would waste significant power.

A critical feature of the Costas Loop is its inherent tolerance to phase ambiguity. In a BPSK Costas Loop, the error detector output is proportional to the sine of twice the phase error (sin(2θ)), not the phase error itself. This means the loop has stable lock points at both 0° and 180°. While the loop locks, there is a 180-degree phase ambiguity in the recovered carrier, which is resolved by using differential encoding of the data at the transmitter. This prevents catastrophic data inversion.

The classic Costas Loop uses two parallel arms: the In-Phase (I) arm and the Quadrature (Q) arm. The local Voltage-Controlled Oscillator (VCO) feeds the I-arm directly and the Q-arm through a 90-degree phase shifter. Both arms mix the incoming signal down to baseband. The outputs of the I and Q arms are then multiplied together in the phase detector. The product of these two baseband signals yields a DC term proportional to the phase error, which is filtered and fed back to control the VCO, closing the loop.

Costas Loops can be implemented in analog hardware or digitally in an FPGA or DSP. A digital Costas Loop offers superior precision and flexibility. Key digital components include:

• Numerically Controlled Oscillator (NCO): Replaces the analog VCO.
• Direct Digital Synthesizer (DDS): Generates the precise sine and cosine mixing signals.
• Loop Filter: A digital proportional-integral (PI) controller that defines the loop's dynamic behavior, including its damping factor and natural frequency. Digital loops avoid DC offset and component drift issues common in analog designs.

The loop filter is the control system's brain, defining the trade-off between acquisition speed and phase noise rejection. It is typically a second-order filter. Key design parameters include:

• Noise Bandwidth (BL): A narrow bandwidth filters more noise but slows acquisition. A wider bandwidth locks faster but results in a noisier recovered carrier.
• Damping Factor (ζ): Usually set near 0.707 for a critically damped response, balancing fast settling with minimal overshoot. The filter integrates the phase error to drive the steady-state phase error to zero, ensuring coherent demodulation.

For QPSK and higher-order QAM, the basic Costas Loop is modified. A QPSK Costas Loop requires additional logic to handle the four-phase ambiguity (0°, 90°, 180°, 270°). This is often achieved using a hard-limited Costas Loop or a digital decision-directed variant. The error detector uses the sign of the I and Q data decisions to strip the modulation, generating an error signal proportional to sin(4θ). This ensures stable lock points at multiples of 90 degrees, which are again resolved through differential encoding.