Sampling Clock Jitter

Jitter causes the analog-to-digital converter (ADC) to sample the input waveform at aperiodic intervals rather than the ideal uniform rate. This timing uncertainty modulates the sampled amplitude, as the signal value is captured at a slightly incorrect instant. The resulting error is signal-dependent: the voltage error is proportional to the signal's slew rate at the sampling moment. This creates a noise floor that is not purely random but correlated with the input signal's derivative, producing a unique distortion signature tied to the specific clock source's phase noise profile.

The noise introduced by jitter is not spectrally flat. Its power spectral density is shaped by the phase noise mask of the sampling clock's local oscillator. Key characteristics include:

• Close-in phase noise causes a raised noise pedestal near strong signal tones.
• Reference clock spurs create discrete, narrowband noise peaks at specific offset frequencies.
• The overall noise floor tilt and spur pattern form a highly distinctive spectral signature that can be isolated from thermal noise using long-duration captures.

Clock jitter imposes a fundamental limit on achievable Signal-to-Noise and Distortion Ratio (SINAD). For a given input frequency f_in and RMS jitter t_j, the theoretical SNR ceiling is: SNR = -20 log₁₀(2π f_in t_j). This degradation is deterministic for a given clock source. Two ADCs with identical datasheet specifications but different physical clock modules will exhibit measurably different SNR vs. input frequency curves, providing a distinguishing metric for hardware identification.

The sampling clock's phase noise is directly transferred to the digitized output. Any random frequency fluctuation in the clock oscillator modulates the sampling instant, imprinting the clock's complete phase noise profile onto the captured data. This mechanism is highly effective for fingerprinting because:

• The clock is often a free-running oscillator whose phase noise is dominated by its unique physical resonator and active circuitry.
• This signature persists regardless of the signal being sampled, acting as a persistent hardware watermark on all digitized waveforms.

The jitter characteristics of a clock source are not perfectly static. They exhibit slow temporal variation due to environmental and physical factors:

• Temperature sensitivity: Crystal oscillators have a frequency-temperature curve; phase noise profiles shift with ambient temperature changes.
• Aging effects: Long-term mechanical stress and contamination in the resonator cause a gradual drift in oscillation frequency and an increase in phase noise floor.
• Supply voltage pushing: Fluctuations in the oscillator's power supply modulate its frequency, introducing low-frequency jitter wander. Robust fingerprinting systems must implement drift compensation algorithms to track these slow changes.

While both are ADC non-idealities, jitter noise and quantization error have fundamentally different statistical behaviors:

• Quantization error is bounded (±0.5 LSB) and uniformly distributed for complex signals. Its power is fixed by the converter's bit depth.
• Jitter noise is unbounded in amplitude, signal-dependent, and its power increases with input frequency. Its distribution reflects the clock's phase noise statistics. This distinction allows a fingerprinting system to isolate the jitter contribution by analyzing the noise floor's dependence on input signal frequency and amplitude, separating the clock's unique signature from the ADC's static non-linearity.

The frequency-domain representation of clock jitter, describing the random phase fluctuations of an oscillator signal. It is measured in dBc/Hz at various offsets from the carrier.

• Directly modulates onto the sampled signal, spreading its spectrum
• Integrated phase noise determines total RMS jitter
• Each oscillator exhibits a unique phase noise mask usable for hardware fingerprinting

The sample-to-sample variation in the exact instant a sample-and-hold circuit captures the analog input. This is the physical mechanism by which clock jitter translates into amplitude error.

• Amplitude error = slope of input signal × aperture jitter
• High-frequency inputs suffer disproportionately
• Specified in femtoseconds for high-performance ADCs

Clock jitter imposes a fundamental limit on achievable SNR that cannot be overcome by increasing converter resolution.

• Theoretical SNR limit: SNR = -20 log₁₀(2π · f_in · t_jitter)
• For a 100 MHz input with 1 ps jitter, SNR ceiling ≈ 64 dB
• This jitter-induced noise floor is device-specific, aiding fingerprinting

The cumulative deviation of a digital-to-analog converter's transfer function from an ideal straight line. While distinct from jitter, INL interacts with timing errors to produce complex distortion signatures.

• INL creates amplitude-domain errors; jitter creates time-domain errors
• Combined effect produces unique waveform distortions per device
• Both are exploited simultaneously in advanced RF fingerprinting systems

A discrete spectral tone appearing at an offset from the carrier equal to the reference oscillator frequency. It results from imperfect filtering in the phase-locked loop that multiplies the reference to the sampling clock.

• Spurs are deterministic, not random like jitter
• Their amplitude and exact frequency offset are hardware-specific
• Spurs and jitter together form a rich, identifying spectral signature

The combined effect of semiconductor fabrication variability, supply voltage fluctuations, and operating temperature on transistor performance. PVT variation is the root cause of why each clock source exhibits unique jitter characteristics.

• Threshold voltage mismatches in CMOS inverters create distinct jitter profiles
• Temperature changes cause drift in jitter magnitude over time
• Supply noise couples into the clock path with device-specific sensitivity