PLL Lock Time Signature

The total time required for the PLL to achieve phase lock within a specified error tolerance. This duration is highly sensitive to loop bandwidth and damping factor, which shift due to passive component tolerances in the loop filter.

• Capacitor tolerance: ±5% variation shifts the pole location, altering lock speed.
• Resistor variation: Directly impacts the zero in the loop filter transfer function.
• Charge pump current mismatch: Differences between source and sink currents change the effective loop gain, accelerating or decelerating lock.

Two identical VCOs from the same wafer lot can exhibit settling times differing by 15-20% due to these cumulative analog variances.

The peak amplitude of the frequency excursion beyond the final locked value before settling. The percent overshoot is a direct function of the loop's phase margin, which is altered by component parasitics and VCO gain (Kvco) non-linearity.

• Phase margin degradation: Parasitic capacitance on the loop filter reduces phase margin, increasing overshoot.
• VCO gain slope: A steeper Kvco near the target frequency causes a larger frequency overshoot for a given tuning voltage step.
• Asymmetric recovery: The rate at which the loop recovers from overshoot versus undershoot reveals charge pump current mismatches.

This transient ringing pattern acts as a damped sinusoidal signature unique to each synthesizer IC.

The precise path the VCO frequency traces from its initial unlocked state to the target lock frequency. This trajectory is not a smooth exponential; it contains micro-step discontinuities caused by the discrete nature of the phase-frequency detector (PFD) and charge pump.

• Dead-zone effects: The PFD's inability to resolve very small phase errors creates a flat spot in the trajectory near lock, the width of which varies per device.
• Cycle slipping signatures: If the initial frequency error is large, the PLL may slip cycles, creating a distinct sawtooth pattern in the frequency ramp whose period reflects the specific VCO tuning sensitivity.
• Reference spur modulation: Leakage of the reference clock onto the tuning line superimposes a small periodic ripple on the trajectory.

The moment the PLL's internal lock detector asserts its output is not instantaneous; it generates a characteristic glitch or transient disturbance on the tuning voltage as the loop transitions from acquisition to tracking mode.

• Charge pump mode switching: Many PLLs switch charge pump current from a high-gain acquisition mode to a low-noise tracking mode, causing a voltage step on the loop filter.
• Lock detector hysteresis: The voltage threshold and timing window used to declare lock vary with silicon process, creating a device-specific delay and glitch amplitude.
• Post-lock ringing: The disturbance from the lock detection event itself can re-excite the loop, causing a secondary, smaller ringing pattern that decays with the loop's natural damping.

The lock time signature is not static; it shifts predictably with junction temperature, providing a multi-dimensional fingerprint that can be modeled for robust authentication across thermal environments.

• VCO temperature drift: The VCO's free-running frequency shifts with temperature, changing the initial frequency error and thus the lock trajectory length.
• Loop filter tempco: The temperature coefficient of the loop filter's resistors and capacitors (e.g., X7R vs. C0G dielectrics) alters the loop dynamics, changing overshoot and settling time.
• Charge pump current drift: Bandgap reference circuits have a parabolic temperature response, causing the charge pump current to vary by 1-3% over the industrial temperature range.

Characterizing the lock signature across a thermal profile yields a unique 3D surface for each device.

The PLL's lock behavior exhibits a measurable dependence on the power supply rail voltage, creating a voltage-dependent signature that reflects the power supply rejection ratio (PSRR) of the analog blocks.

• VCO pushing: The VCO frequency shifts directly with supply voltage changes, altering the initial frequency error at lock start.
• Charge pump headroom: Reduced supply voltage compresses the charge pump's output compliance range, distorting the tuning voltage ramp near the rails.
• PFD delay variation: The propagation delay of the phase-frequency detector's logic gates changes with supply voltage, altering the dead-zone characteristics and the fine structure of the lock trajectory.

This sensitivity provides an additional orthogonal dimension for distinguishing devices operating under varying battery conditions.

The short-term random frequency fluctuations in a transmitter's master oscillator that modulate onto the carrier. While PLL lock time captures the macroscopic transient, phase noise defines the microscopic, steady-state spectral purity. The loop filter design that determines lock time directly trades off against phase noise suppression. A wider loop bandwidth accelerates lock time but admits more reference and VCO noise, creating a device-specific equilibrium point.

A discrete spectral tone appearing at an offset equal to the reference oscillator frequency from the carrier. This spur results from imperfect filtering of the reference signal in the phase-frequency detector (PFD) and charge pump. The amplitude of this spur is directly influenced by the PLL's lock dynamics—specifically, the charge pump current mismatch and loop filter settling behavior during the acquisition phase.

The frequency shift of an oscillator caused by load impedance changes during modulation. This dynamic frequency trajectory is distinct from the initial lock transient but shares the same underlying sensitivity. A VCO with high pulling sensitivity will exhibit both a more complex lock time signature and greater frequency drift during burst transmission, linking the turn-on transient to steady-state modulation fidelity.

The broader discipline of extracting identifying features from the brief turn-on and turn-off periods of a transmitter's signal burst. PLL lock time signature is a primary component of this analysis, alongside power amplifier ramp characteristics and modulator settling. The complete transient envelope—including frequency overshoot, settling time, and damping factor—forms a multidimensional fingerprint that is difficult to clone.

The combined effect of semiconductor fabrication variability, supply voltage fluctuations, and operating temperature on transistor performance. These variations directly impact the analog components within a PLL—specifically the VCO gain (Kvco), charge pump current, and loop filter time constants. Each chip's unique PVT profile produces a distinct lock time signature, making it a reliable hardware fingerprint.

The algorithms that track and adjust for the slow temporal variation of hardware impairments due to temperature and aging. A PLL's lock time signature will drift as the loop filter capacitors age and the VCO's tuning sensitivity shifts. Robust fingerprinting systems must model this drift to maintain authentication accuracy over the device's operational lifetime.