Transient DC Offset

The transient DC offset primarily originates from the differential baseband amplifiers in the IQ modulator. During power-up, these amplifiers exhibit a momentary imbalance in their bias voltages as the internal current sources and active loads stabilize. This imbalance manifests as a non-zero DC voltage at the modulator input, which directly translates to local oscillator (LO) feedthrough at the RF output. The settling time and initial offset magnitude are dictated by the amplifier's common-mode rejection ratio (CMRR) and the matching of its input transistors.

The direct consequence of transient DC offset is a distinct, narrowband spectral spike at the exact carrier frequency. This carrier feedthrough is independent of the intended modulation and appears as an unmodulated tone. Key characteristics include:

• Amplitude: Directly proportional to the magnitude of the DC offset voltage.
• Duration: Matches the settling time of the baseband circuitry, typically lasting microseconds.
• Phase: The phase of the leaked carrier is fixed relative to the LO and is a unique hardware identifier.

While all direct-conversion modulators exhibit some degree of steady-state LO leakage due to permanent component mismatches, the transient DC offset is a dynamic, time-varying phenomenon. The steady-state leakage is a constant artifact, whereas the transient version is a momentary burst during the ramp-up. This temporal distinction is critical for fingerprinting, as the dynamic behavior reveals the settling dynamics of the bias circuits, providing a richer feature set than a static leakage measurement.

The transition of the digital-to-analog converter (DAC) from a zero-output code to the first modulation sample is a primary trigger. A non-ideal DAC exhibits a glitch impulse during this major code transition, which is coupled to the modulator output. This glitch energy is not a true DC offset but a fast impulse that can be integrated by the modulator's bandwidth limitations, appearing as a momentary DC bias. The glitch area and shape are unique to the DAC's internal switch timing skews.

The magnitude and settling profile of the transient DC offset are highly sensitive to junction temperature and supply voltage. A cold-start transient will exhibit a different offset profile than a warm re-key, as the semiconductor bandgap and bias currents are temperature-dependent. Similarly, the power supply rejection ratio (PSRR) of the baseband amplifiers dictates how supply rail fluctuations during inrush current modulate the offset. This creates a multi-dimensional signature tied to the device's physical state.

The transient DC offset is visualized as a shift of the IQ constellation centroid away from the origin during the burst onset. By plotting the sampled I and Q components over time, the trajectory of the centroid from (0,0) to its steady-state bias point is revealed. The vector magnitude and angle of this shift over the first few microseconds form a robust feature. This trajectory is extracted by averaging the IQ samples within a sliding window synchronized to the burst onset detection point.