Trailing Edge Jitter

The primary physical mechanism behind trailing edge jitter is the discharge behavior of decoupling capacitors and the parasitic inductance of the power distribution network (PDN). As the power amplifier (PA) is switched off, the collapsing current draw induces a voltage transient on the supply rail. The specific impedance of the decoupling network—dominated by equivalent series resistance (ESR) and equivalent series inductance (ESL)—dictates the exact timing of the final logic transition. Variations in capacitor aging, dielectric absorption, and solder joint quality create a unique, device-specific jitter signature that is extremely difficult to clone.

The trailing edge is defined by the final switching event of a digital buffer or gate driver. The propagation delay (t_pd) through these CMOS gates is a function of instantaneous threshold voltage (V_th), channel mobility, and temperature. During the power-down sequence, the supply voltage is not stable but is collapsing, causing the gate to operate in a non-linear, sub-threshold region. This makes the exact switching moment highly sensitive to microscopic doping inconsistencies and oxide trap charges within the semiconductor lattice, imprinting a physically unclonable function (PUF)-like characteristic onto the jitter.

It is critical to distinguish between fall-time variance and trailing edge jitter.

• Fall-time variance: The statistical distribution of the 90% to 10% amplitude collapse duration. This is an analog metric tied to the slew rate of the discharge path.
• Trailing edge jitter: The temporal displacement of the entire falling edge relative to an ideal clock reference. This is a discrete timing error. While fall-time variance contributes to the shape of the turn-off transient, jitter specifically measures the phase noise of the burst offset, providing a distinct, orthogonal feature for neural network classifiers.

Jitter on the trailing edge is not solely a local effect; it is heavily influenced by the clock distribution tree. As the clock signal propagates through the device to the final output register, it accumulates random jitter (RJ) from thermal noise and deterministic jitter (DJ) from crosstalk and power supply induced jitter (PSIJ). The trailing edge captures the cumulative effect of this clock jitter at the exact moment of de-assertion. The phase noise profile of the reference oscillator is directly sampled and embedded into the timing of the burst offset, making it a high-fidelity identifier of the clock synthesis chain.

Extracting trailing edge jitter requires high-precision zero-crossing analysis on the captured IQ data. The process involves:

1. Burst Offset Detection: Precisely locating the sample point where the signal envelope drops below the noise floor.
2. Interpolation: Using sinc interpolation to upsample the region around the final zero-crossing, achieving sub-sample time resolution.
3. Histogram Generation: Collecting the precise timing of the last zero-crossing over thousands of bursts to build a jitter histogram. The standard deviation and peak-to-peak spread of this histogram form the raw jitter fingerprint.

Trailing edge jitter is exceptionally resistant to adversarial spoofing because it is a passive, physics-enforced artifact. An attacker cannot easily manipulate the power supply decoupling network or the semiconductor physics of their transmitter to match a target's jitter profile. Unlike steady-state frequency errors which can be corrected with a pre-distorted waveform, the stochastic nature of the power-down sequence is governed by chaotic, temperature-sensitive interactions. Any active attempt to inject a false jitter pattern typically introduces its own distinct artifacts, making the spoofing attempt detectable by a trained open set recognition model.