Ramp-Down Signature

The core of the ramp-down signature is the exponential or linear decay of the signal envelope. This profile is governed by the RC time constant of the power supply decoupling network. The precise rate at which stored energy in bypass capacitors and the power amplifier's bias circuitry depletes creates a unique, repeatable voltage sag that directly amplitude-modulates the trailing edge of the burst.

As the transmitter shuts off, an abrupt, unintended shift in the instantaneous phase of the carrier signal often occurs. This phase discontinuity is caused by the non-ideal switching of the frequency synthesizer and the rapid change in the power amplifier's input impedance. The magnitude and direction of this phase jump are highly repeatable and specific to the transmitter's semiconductor physics.

The 90% to 10% fall time is not a fixed constant but a statistical distribution. Fall-time variance captures the stochastic nature of the discharge path. Minute differences in thermal noise, semiconductor lattice defects, and capacitor dielectric absorption cause microsecond-level variations in the ramp-down duration across multiple bursts, providing a robust statistical fingerprint.

Immediately following the ramp-down, the signal often dips below the noise floor before recovering. This undershoot is followed by a damped sinusoidal oscillation (ringing) caused by parasitic inductance and capacitance in the output matching network resonating. The resonant frequency and the exponential decay constant of this damped oscillation profile are distinct hardware signatures.

When the high-current draw of the transmission ceases, the power supply regulator experiences a momentary rebound effect. The control loop, tuned for a specific load, overshoots its target voltage. This transient over-voltage briefly changes the bias point of any still-active circuits, creating a subtle but measurable distortion in the final microseconds of the trailing edge.

The precise moment the signal burst ends is not deterministic. Trailing edge jitter is the temporal instability in the falling edge's exact timing, caused by asynchronous logic gate propagation delays and clock distribution imperfections. This timing variation, measured against a reference clock, serves as a unique identifier of the digital control circuitry.