PLL Overshoot

The damping factor (ζ) of the PLL's loop filter directly dictates the overshoot magnitude. An underdamped loop (ζ < 1) produces a characteristic frequency ringing and peak overshoot proportional to the filter's component tolerances. Key points:

• Overshoot percentage is mathematically related to ζ by: %OS = 100 * exp(-ζπ / sqrt(1-ζ²))
• A ζ of 0.5 yields ~16% overshoot; ζ of 0.3 yields ~37%
• Passive loop filter capacitors and resistors have 5-20% manufacturing tolerances, making ζ a unique hardware identifier
• The exact overshoot peak reveals the ratio of the loop filter's time constants (τ₁/τ₂)

Mismatch between the charge pump's source and sink currents creates an asymmetric loop response, distorting the overshoot profile during acquisition. Artifacts include:

• Asymmetric overshoot: different peak excursions for upward vs. downward frequency transitions
• Static phase offset at lock, which shifts the entire settling trajectory
• Current mismatch of even 1-2% in CMOS charge pumps produces measurable fingerprint features
• The mismatch is caused by random variations in transistor threshold voltages (Vth) and channel length modulation

The voltage-controlled oscillator gain (KVCO) — measured in Hz/V — varies from unit to unit due to process variations in the varactor and inductor. This variability directly scales the overshoot amplitude. Impact on fingerprinting:

• A higher KVCO amplifies the voltage step from the loop filter, increasing the peak frequency excursion
• KVCO non-linearity across the tuning range creates a channel-dependent overshoot signature
• Typical KVCO variation is ±10-15% across a production batch, providing strong inter-device discrimination
• The overshoot-to-KVCO relationship is: Δf_peak ∝ KVCO * ΔV_control

During the transient locking period, reference frequency spurs appear as modulation sidebands on the overshoot peak. These spurs are caused by leakage of the reference clock into the VCO control line. Fingerprinting features:

• Spur amplitude and phase relative to the carrier are unique per device
• PCB layout parasitics and decoupling effectiveness determine spur magnitude
• The transient spur profile often differs from steady-state spurs due to dynamic bias conditions
• Spur frequency offset equals the phase detector comparison frequency (F_ref)

There exists a fundamental trade-off between settling time and overshoot that is uniquely balanced in each device. A device with a wider loop bandwidth settles faster but exhibits more overshoot. Measurable parameters:

• The product of overshoot percentage and settling time is a device-specific constant
• Settling time to within ±1 ppm of final frequency typically ranges from 50-500 µs
• The exponential decay envelope of the overshoot ringing reveals the loop's dominant pole location
• Temperature changes shift this balance predictably, enabling temperature-compensated fingerprinting

The phase margin of the open-loop transfer function determines the overshoot and ringing characteristics. Phase margin is set by the loop filter's pole-zero placement, which varies with component tolerances. Fingerprint indicators:

• Phase margin < 45° produces excessive ringing with multiple overshoot cycles
• Phase margin of 60° yields a single, well-defined overshoot peak (ideal for fingerprinting)
• The number of ringing cycles before settling is a discrete, countable feature
• The Q-factor of the closed-loop response is inversely proportional to phase margin

The complete time-domain response of the phase-locked loop as it acquires lock, including frequency overshoot and phase error convergence. This transient is highly dependent on component tolerances in the loop filter, making it a rich source of identifying features. The settling profile reveals the exact damping factor and natural frequency of the control system.

The trajectory of the instantaneous carrier frequency as it converges to its steady-state value after activation. Key features include:

• Peak overshoot magnitude: The maximum frequency excursion beyond the target
• Settling time: Duration to stabilize within a specified tolerance (e.g., ±1 kHz)
• Ringing frequency: The oscillation rate of the damped response These parameters directly expose the loop filter capacitor and resistor values.

The dynamic behavior of the voltage-controlled oscillator during the start-up period, including frequency pushing (sensitivity to supply voltage changes) and frequency pulling (sensitivity to load impedance changes). The VCO's transient imprints a unique signature on the carrier as the tuning voltage slews toward lock. Thermal transients in the VCO's resonator also cause a characteristic instantaneous frequency drift.

The duration required for a phase-locked loop to synchronize with a reference signal after power-up. This critical transient period exposes the loop's dynamic characteristics for fingerprinting. Lock time is a function of:

• Loop bandwidth: Wider bandwidths lock faster but with more overshoot
• Phase margin: Lower margins cause more ringing before settling
• Reference frequency: Higher references enable faster phase comparisons Variations in lock time across devices indicate component aging and manufacturing variance.

A temporary elevation in the phase noise spectrum of the local oscillator during the transient locking period. Before the loop stabilizes, the phase detector and charge pump inject elevated noise into the VCO control line. This creates a unique noise signature characterized by:

• Burst duration: Typically microseconds to milliseconds
• Peak noise density: Often 10-20 dB above steady-state levels
• Spectral shape: Reflects the loop filter's noise transfer function The burst profile serves as a distinct hardware identifier before the loop reaches steady state.

The measurement of the duration required for a transmitter's frequency and amplitude to stabilize within a specified tolerance after the initial turn-on event. This analysis reveals PLL dynamics and power supply regulation characteristics. Key metrics include:

• Frequency settling: Time to reach ±1 ppm of target frequency
• Amplitude settling: Time to reach ±0.1 dB of steady-state power
• Phase settling: Time for residual phase error to converge Settling time distributions across multiple bursts provide a statistical fingerprint of the device's control loop components.