PLL Lock Time

The time-domain trajectory of the VCO frequency as it converges to the target. This profile reveals the loop filter transfer function and component values.

• Key metrics: Settling time to within 1 ppm, peak frequency overshoot, and number of ringing cycles
• Fingerprinting value: The exact damping factor and natural frequency are determined by resistor-capacitor tolerances unique to each device
• Example: A Type-II third-order PLL with 5% component tolerance produces a settling profile distinguishable across otherwise identical radios

The peak frequency excursion beyond the target lock frequency during acquisition. This overshoot is a direct indicator of the loop's damping factor (ζ) and phase margin.

• Caused by the charge pump injecting excess current into the loop filter during the initial phase error correction
• Underdamped loops (ζ < 0.7) exhibit significant overshoot with visible ringing, while overdamped loops converge monotonically
• The exact overshoot percentage is sensitive to charge pump current mismatch and loop filter capacitor dielectric absorption

A temporary elevation in phase noise during the transient locking period, creating a unique noise signature before the loop stabilizes.

• The loop's in-band phase noise is dominated by reference oscillator and phase detector noise, while out-of-band noise reflects VCO free-running characteristics
• During lock acquisition, the loop bandwidth effectively widens, allowing VCO noise to leak through momentarily
• Fingerprinting feature: The time-varying phase noise power spectral density during the first 200 µs of locking

The dynamic behavior of the voltage-controlled oscillator during start-up, including frequency pushing and pulling effects that imprint a unique signature on the carrier.

• Frequency pushing: VCO frequency shift due to supply voltage transients during power amplifier turn-on
• Frequency pulling: VCO frequency deviation caused by sudden impedance changes at the output load
• The VCO's tuning sensitivity (Kvco) and varactor non-linearity create a device-specific mapping between control voltage and output frequency during the transient

The total energy contained in momentary, unintended frequency hops or spurious outputs generated by the frequency synthesizer during the lock acquisition.

• Caused by fractional-N spur generation, charge pump non-idealities, and sigma-delta modulator quantization noise during the transient
• Glitch energy is computed by integrating the spurious power over the lock time duration
• Device-specific: The exact glitch pattern depends on the synthesizer's digital logic timing skews and analog mismatch

The dielectric absorption effect in the loop filter capacitors that causes the PLL's settling behavior to depend on its previous locked state.

• Capacitors with high dielectric absorption (e.g., X7R ceramics) exhibit voltage memory that shifts the initial loop filter voltage at the next power-up
• This creates a history-dependent transient signature where the lock time and overshoot vary based on the prior frequency and duration of operation
• The effect is quantified by the capacitor's dielectric absorption ratio (typically 0.1-5%)

The complete time-domain response of a phase-locked loop as it acquires lock after power-up or a channel change. This transient period includes frequency overshoot, phase error convergence, and loop filter stabilization. The specific trajectory of this settling process is highly dependent on the tolerances of passive components—such as capacitors and resistors in the loop filter—making it a rich source of unique hardware fingerprints. Unlike steady-state operation, the settling transient exposes the dynamic non-linearities of the voltage-controlled oscillator (VCO) and the charge pump, which are dominated by manufacturing variances.

The trajectory of the instantaneous carrier frequency as it converges to its steady-state target value. This profile is a direct window into the loop filter characteristics and the damping factor of the PLL. Key features include:

• Pull-in time: The duration to reduce the initial frequency error to near zero.
• Lock-in time: The final phase acquisition period.
• Overshoot magnitude: The peak frequency excursion beyond the target. Variations in these parameters, caused by component aging and thermal effects, create a distinct signature for each transmitter.

The peak frequency excursion beyond the target lock frequency during the PLL's acquisition process. This is a direct indicator of the loop filter's damping factor and the VCO's gain sensitivity (Kvco). An underdamped loop will exhibit a high overshoot and subsequent ringing artifact, while an overdamped loop will settle monotonically. The exact percentage of overshoot and the number of ringing cycles are deterministic hardware traits that can be measured and used for emitter identification, as they are set by the physical values of the loop components.

A temporary elevation in the phase noise spectrum of the local oscillator during the transient locking period. Before the loop stabilizes, the VCO's control voltage is fluctuating, leading to a short-term increase in random frequency modulation. This burst creates a unique noise signature that differs from the steady-state phase noise floor. The duration and spectral shape of this burst are influenced by the loop bandwidth and the charge pump current, providing a distinct, time-limited feature for transient fingerprinting.

The precise measurement of the duration required for a transmitter's frequency and amplitude to stabilize within a specified tolerance (e.g., ±1 ppm) after the initial turn-on event. This analysis quantifies the dynamic response of the entire synthesis chain. Key metrics include:

• Frequency settling time: Time to reach final frequency.
• Phase settling time: Time to achieve phase coherence.
• Amplitude settling time: Time for the power envelope to stabilize. These durations are statistically unique per device due to component tolerances.

The path traced by the instantaneous phase of a signal in the complex (I/Q) plane during the PLL lock period. As the loop acquires lock, the phase error converges from an arbitrary initial value to a steady-state offset. This trajectory reveals the underlying dynamics of the loop filter and VCO. The shape of this convergence path—whether it spirals in, overshoots, or follows a direct vector—is a high-dimensional feature used in deep learning models for emitter classification, as it captures the non-linear interaction between the phase detector and the VCO.