ADC Jitter Simulation

The statistical probability density function (PDF) governing the random timing error applied to each sampling instant. The standard model is a zero-mean Gaussian distribution, where the standard deviation (σ_j) directly represents the RMS jitter in seconds. This accurately emulates the thermal noise-induced jitter in real phase-locked loops (PLLs). For simulating deterministic jitter from power supply ripple, a sinusoidal jitter model with a specific frequency and amplitude is injected. The choice of distribution critically impacts the resulting Signal-to-Noise Ratio (SNR) degradation, with Gaussian jitter producing a noise floor and sinusoidal jitter creating distinct spurious tones in the spectrum.

The RMS jitter value, typically specified in femtoseconds (fs) or picoseconds (ps), directly imposes a fundamental, irreducible limit on a data converter's SNR. This relationship is defined by the equation: SNR_jitter = -20 log₁₀(2π * f_in * σ_j), where f_in is the analog input frequency. For a high-speed ADC sampling a 1 GHz input, an RMS jitter of just 100 fs caps the theoretical SNR at approximately 44 dB. This parameter is the primary knob for stress-testing a fingerprinting model's resilience to timing uncertainty, as it dictates the noise floor of the entire digital twin.

The frequency-domain characteristic of the jitter process, defining how timing error power is distributed across the spectrum. A white jitter model assumes a flat power spectral density, injecting uncorrelated errors sample-to-sample. A more realistic model uses a flicker jitter profile (1/f noise), where low-frequency phase noise dominates, causing slow, correlated wander of the sampling clock. This spectral shape is derived from a phase noise mask (dBc/Hz vs. offset frequency) and is critical for accurately replicating the close-in phase noise that distorts OFDM subcarrier orthogonality.

The simulated topology of the clock generation circuit, which determines the jitter's origin and characteristics. A common clock source simulation applies identical jitter to both the transmitter's DAC and receiver's ADC, causing correlated errors that may partially cancel. A distributed clock architecture simulates independent, uncorrelated jitter sources for the transmitter and receiver, representing a more challenging and realistic scenario for a fingerprinting model. This parameter defines whether the jitter manifests as a common-mode or differential impairment in the end-to-end signal chain.

A critical distinction in simulation parameterization. Aperture delay is the fixed, nominal time offset between the sampling clock edge and the instant the sample is actually taken; it is a constant latency that does not degrade SNR. Aperture uncertainty (jitter) is the sample-to-sample random variation around this delay. A robust simulation must model the latter as a dynamic stochastic process while treating the former as a static timing offset that can be trivially calibrated out. Confusing these two parameters leads to an incorrect noise model.

The relationship between the ADC's sampling frequency (Fs) and the jitter's impact. For a given RMS jitter, the SNR penalty is independent of the sampling rate but is highly dependent on the input signal frequency. However, in an oversampled system, the quantization noise is spread over a wider bandwidth, but the jitter-induced noise floor remains fixed. This parameter is crucial for simulating undersampling architectures, where the ADC intentionally samples a high-frequency signal at a rate far below the Nyquist criterion, making the system exquisitely sensitive to picosecond-level timing errors.

Aperture uncertainty is the random variation in the exact instant a sample-and-hold circuit captures a signal. In simulation, this is modeled as a Gaussian-distributed timing error added to the ideal sampling clock edge. The resulting voltage error is proportional to the signal's slew rate: a fast-changing signal sampled with jitter produces a larger amplitude error than a slow one. This effect directly degrades the signal-to-noise ratio (SNR) and introduces a noise floor that scales with input frequency.

ADC jitter in the time domain is the dual of phase noise in the frequency domain. A sampling clock with a known phase noise mask (dBc/Hz vs. offset frequency) can be converted to an equivalent RMS jitter value by integrating the phase noise over a specific bandwidth. This allows a simulator to generate consistent impairments whether modeling the clock source in the frequency domain or the sampling error in the time domain.

Jitter-induced noise is not purely random; its interaction with the signal creates subtle, structured artifacts that can become device-specific identifiers. Key effects include:

• Constellation smearing: Points in I/Q space blur radially, with outer points exhibiting greater variance.
• Spectral regrowth mimicry: Though distinct from PA non-linearity, jitter can produce similar out-of-band artifacts at high frequencies.
• SNR-dependent feature reliability: Features extracted from high-slew-rate signal segments become less reliable as jitter increases.

In a complete digital twin pipeline, ADC jitter simulation must be combined with DAC quantization error modeling. The transmitter's DAC introduces discrete amplitude steps, while the receiver's ADC adds both quantization and jitter. The interplay is critical: jitter can mask quantization spurs by spreading their energy, while coarse quantization can dominate the error budget and obscure jitter effects. Realistic simulators apply these impairments sequentially in the correct order of the signal chain.

Practical jitter simulation requires modeling the clock source itself. Common approaches include:

• White jitter model: A simple Gaussian distribution with a single RMS value, suitable for thermal-noise-limited clocks.
• Flicker jitter model: Incorporates 1/f noise characteristics for low-offset-frequency phase noise.
• Phase noise mask playback: Directly uses measured or specified phase noise profiles to generate time-domain jitter sequences via inverse Fourier transform.
• Spurious tone injection: Adds deterministic jitter from known interferers like power supply ripple.

A synthetic jitter model is validated by comparing its output to real hardware captures. Key metrics include:

• Achieved SNR vs. input frequency: The simulated SNR degradation curve must match the ADC's datasheet specification.
• Jitter histogram: The distribution of simulated timing errors should match the measured distribution from a real clock.
• Eye diagram closure: For digital modulation, the simulated jitter must produce the same eye opening degradation as the physical device under test.