DAC Offset Error

DAC offset error is the non-zero analog output voltage produced when the digital input code is set to zero (or mid-scale for bipolar operation). It originates from transistor mismatch, current mirror inaccuracies, and reference voltage drift within the DAC's internal architecture. Unlike random noise, this is a deterministic, static error that remains consistent for a given device under fixed environmental conditions, making it a reliable feature for physical layer identification.

In a direct-conversion transmitter, DAC offset error manifests as a rigid translation of the entire constellation diagram away from the (0,0) origin. This is mathematically equivalent to adding a constant DC vector to the baseband signal:

• I-path offset: Shifts the constellation horizontally
• Q-path offset: Shifts the constellation vertically
• Combined offset: Produces a diagonal displacement

The resulting origin point offset is a primary contributor to carrier leakage in zero-IF architectures, creating an unmodulated spur at the local oscillator frequency.

DAC offset error is a high-value fingerprinting feature because:

• Uniqueness: Each DAC exhibits a distinct offset due to random manufacturing variations in its internal current sources and resistor ladders
• Stability: The offset remains highly stable over short timeframes under constant temperature, enabling reliable re-identification
• Independence: The I and Q DACs in a transceiver typically have uncorrelated offset errors, doubling the fingerprinting dimensionality
• Universality: Present in virtually all practical DAC implementations, from low-cost IoT radios to high-end software-defined radios

DAC offset error is typically specified in datasheets and measured in:

• LSB (Least Significant Bits): The offset expressed as a multiple of the DAC's smallest voltage step
• Millivolts (mV): The absolute voltage offset at the analog output
• Percentage of Full-Scale Range (%FSR): Normalized offset relative to the maximum output swing

Measurement requires applying a zero-code digital input and measuring the analog output with a precision voltmeter, ensuring the DAC is isolated from subsequent gain stages that could amplify or mask the intrinsic offset.

While both DAC and ADC offset errors contribute to the overall DC offset in a transceiver chain, they originate at different points:

• DAC offset error: Occurs in the transmit path, adding a static voltage to the generated baseband signal before upconversion
• ADC offset error: Occurs in the receive path, adding a static voltage to the digitized baseband signal after downconversion

In a full-duplex or loopback fingerprinting scenario, these two offsets are additive and inseparable without calibration, forming a combined transmit-receive offset signature.

Although DAC offset error is considered static, it exhibits slow temporal drift due to:

• Temperature coefficient: Offset typically drifts by 1-5 ppm/°C of full-scale range, caused by thermal gradients across the die
• Component aging: Long-term shifts in transistor threshold voltages and resistor values over thousands of operating hours
• Supply voltage sensitivity: Offset variation with power supply fluctuations, quantified by power supply rejection ratio (PSRR)

These drift mechanisms necessitate periodic re-calibration or adaptive tracking algorithms in long-term fingerprinting deployments.