Direct RF Sampling

Traditional superheterodyne receivers use multiple mixer stages and local oscillators to step down the RF frequency to an intermediate frequency (IF) before digitization. Direct RF sampling connects the analog-to-digital converter (ADC) directly to the antenna, bypassing these analog components entirely. This removes sources of I/Q imbalance, LO leakage, and phase noise inherent in analog mixers, resulting in a cleaner, more mathematically pure signal representation for downstream AI processing.

Direct RF architectures intentionally exploit aliasing by sampling at rates below the carrier frequency but above twice the signal bandwidth. This technique, known as sub-sampling or bandpass sampling, uses a high-bandwidth sample-and-hold amplifier to capture the RF signal in a higher Nyquist zone. The resulting folded spectrum appears at a lower frequency in the digital domain, effectively performing frequency translation without analog hardware. Key requirements:

• Jitter: Must be below 100 femtoseconds for GHz-range signals
• Analog bandwidth: The ADC's input bandwidth must exceed the carrier frequency, not just the sample rate

Direct RF sampling ADCs produce raw data rates exceeding 100 Gbps for wideband, multi-channel systems. The JESD204B and JESD204C serial interface standards are critical for transporting this torrent of digitized samples to FPGAs or processors. These protocols provide deterministic latency, multi-gigabit lane bonding, and harmonic clocking. For edge AI deployments, the FPGA must ingest this stream, perform digital down-conversion (DDC) and channelization, and feed a real-time inference engine—all within a strict power envelope.

Once the entire RF spectrum is digitized, a Digital Down Converter implemented in FPGA fabric extracts the signal of interest. The DDC performs three operations:

• Numerically Controlled Oscillator (NCO): Generates a digital sinusoid for frequency translation
• Digital Mixer: Multiplies the input samples by the NCO output to shift the target band to baseband
• Cascaded Integrator-Comb (CIC) and FIR decimation filters: Reduce the sample rate and filter out adjacent channels This allows a single wideband digitizer to service multiple virtual receivers simultaneously.

Without analog pre-filtering, the ADC must digitize the entire spectrum including strong interferers alongside weak signals of interest. The Spurious-Free Dynamic Range (SFDR) becomes the critical specification. A high SFDR (e.g., > 80 dBc) ensures that intermodulation products from strong blockers do not create false signals that mask the subtle hardware impairment fingerprints used for device authentication. Modern direct RF ADCs achieve this through advanced dithering techniques and calibration logic integrated on-chip.

For Radio Frequency Fingerprinting at the edge, direct RF sampling provides a pristine, uncompromised digital representation of the raw waveform. This is essential because:

• Transient analysis: Captures the full turn-on burst without analog filter ringing
• Phase preservation: Maintains the exact phase relationships critical for identifying DAC non-linearities and power amplifier memory effects
• Multi-band awareness: A single ADC can simultaneously fingerprint devices operating on different frequencies This architecture enables real-time, physical-layer authentication on embedded platforms like the Xilinx Zynq or NVIDIA Jetson.

A digital signal processing block that converts a digitized band-limited high sample rate signal to a lower sample rate baseband signal. In a direct RF sampling architecture, the DDC is implemented in FPGA fabric or an ASIC immediately after the ADC, performing mixing, filtering, and decimation to reduce the data rate to a level manageable for subsequent processing stages. Modern DDCs use CIC filters, half-band filters, and numerically controlled oscillators (NCOs) to achieve high dynamic range without analog artifacts.

A high-speed serial interface standard used to connect high-bandwidth data converters to logic devices such as FPGAs. Direct RF sampling ADCs operating at multiple gigasamples per second (GSPS) generate data rates exceeding the capabilities of parallel LVDS interfaces. JESD204B/C provides deterministic latency, lane alignment, and multi-device synchronization using SYSREF signals, reducing I/O pin count from hundreds to just a few differential pairs. The C revision supports data rates up to 32 Gbps per lane.

A unidirectional point-to-point protocol within the ARM AMBA specification designed for high-throughput streaming data transfer. In direct RF sampling pipelines, digitized IQ samples flow through the FPGA fabric using AXI4-Stream interfaces between IP cores:

• TDATA: The payload carrying complex samples
• TVALID/TREADY: Handshaking signals for backpressure control
• TKEEP/TLAST: Byte qualifiers and packet boundary markers This protocol enables zero-copy chaining of DDC, filtering, and AI inference blocks without processor intervention.

An operating system designed for deterministic timing constraints, critical for direct RF sampling systems where ADC data must be processed within strict latency budgets. Unlike general-purpose OSes, an RTOS provides:

• Preemptive priority-based scheduling with bounded interrupt latency
• Priority inversion avoidance mechanisms
• Memory locking to prevent paging delays Examples include FreeRTOS, VxWorks, and Zephyr, often running on the processing system of an SoC while the programmable logic handles the high-throughput datapath.

A data management technique where the CPU avoids copying data between memory buffers, instead passing pointers to drastically reduce latency and overhead. In direct RF sampling pipelines, ADC samples are written via DMA directly into a shared memory region accessible by both the FPGA fabric and the processor. The AI inference engine reads from this same buffer without intermediate copies. This is essential when processing multi-gigabit-per-second sample streams where memory bandwidth is the primary bottleneck.

A technique using different numerical precisions for various layers or operations within a single neural network. For edge deployment on direct RF sampling hardware, models are often quantized to INT8 for convolutional layers while keeping attention mechanisms at FP16. This balances:

• Computational speed: INT8 operations execute faster on NPU and FPGA DSP slices
• Accuracy: Sensitive layers retain higher precision to preserve signal fidelity
• Memory bandwidth: Reduced precision decreases the data volume transferred from ADC buffers to the inference engine