Inferensys

Glossary

Speed Bump

An intentional, asymmetric microsecond delay introduced by a trading venue to neutralize the speed advantage of high-frequency traders and protect resting liquidity providers.
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MARKET MICROSTRUCTURE MECHANISM

What is a Speed Bump?

A speed bump is an intentional, asymmetric microsecond delay introduced by a trading venue to neutralize the speed advantage of high-frequency traders and protect resting liquidity providers.

A speed bump is a deliberate, venue-imposed latency delay—typically measured in microseconds—applied asymmetrically to incoming orders or outgoing market data. Unlike the uniform latency of physical colocation, a speed bump selectively slows specific message flows, such as aggressive marketable orders, while allowing cancellations or resting limit orders to bypass the delay. This mechanism disrupts latency arbitrage strategies by preventing high-frequency traders from reacting to stale quotes faster than the venue's own market makers can update their prices, thereby reducing adverse selection risk for passive liquidity providers.

The most prominent implementation is the IEX Exchange's 350-microsecond 'magic shoebox' coiled fiber delay, which applies to all incoming and outgoing messages. Other venues employ asymmetric models, such as slowing only order entry while leaving cancellation messages unimpeded, allowing market makers to quickly withdraw quotes when conditions change. By engineering a level playing field, speed bumps directly address the structural inequity of market fragmentation where speed advantages allow traders to pick off resting orders across venues before the consolidated National Best Bid and Offer (NBBO) updates, reinforcing best execution quality for institutional investors.

Market Microstructure Defense

Key Characteristics of a Speed Bump

A speed bump is an intentional, asymmetric microsecond delay introduced by a trading venue to neutralize the speed advantage of high-frequency traders and protect resting liquidity providers.

01

Asymmetric Delay Mechanism

The defining feature of a speed bump is its asymmetric application. The delay is imposed only on incoming aggressive orders (marketable orders that take liquidity), while resting passive orders (limit orders that provide liquidity) receive real-time market data and can cancel or reprice without delay. This asymmetry specifically targets latency arbitrage strategies that profit from racing to stale quotes before a venue can update them. The delay is typically measured in microseconds (e.g., 350 microseconds on IEX) and is implemented via a coiled fiber optic cable or a software-based delay buffer in the order gateway.

350 µs
Typical Delay Duration
Asymmetric
Delay Application
03

IEX Exchange Implementation

The most famous implementation of a speed bump is on the IEX Exchange, founded by Brad Katsuyama and featured in Michael Lewis's book Flash Boys. IEX's speed bump consists of a 38-mile coiled fiber optic cable that introduces a 350-microsecond delay on all incoming orders before they reach the matching engine. Outgoing market data bypasses the coil, giving resting orders a speed advantage. This physical implementation ensures the delay is deterministic and cannot be bypassed through software optimization. IEX received SEC approval as a national securities exchange in 2016 after a contentious battle with incumbent exchanges.

38 miles
Fiber Coil Length
2016
SEC Exchange Approval
04

Controversy and Market Structure Debate

Speed bumps have generated significant controversy in market structure debates. Proponents argue they level the playing field by preventing technological arms races and protecting long-term investors from predatory HFT strategies. Critics, including major exchanges like NYSE and Nasdaq, contend that speed bumps fragment liquidity, create a two-tiered market, and violate the principle of price-time priority by artificially advantaging certain order types. The SEC has allowed speed bumps but has scrutinized whether they comply with Regulation NMS and the Order Protection Rule, which requires trades to occur at the best available price across all venues.

05

Impact on Queue Position and Fairness

A speed bump fundamentally alters the queue position dynamics of a limit order book. In a traditional price-time priority market, the first order at a given price level is matched first. By delaying aggressive orders while allowing passive orders to cancel instantly, the speed bump effectively gives resting liquidity providers a last-mover advantage. This reduces the risk of adverse selection for market makers, encouraging tighter spreads and deeper liquidity. However, it also means that a trader who is first to respond to new information may be disadvantaged, raising questions about whether speed bumps distort the price discovery process.

06

Global Adoption and Variants

Beyond IEX, several global venues have adopted speed bump mechanisms with varying designs:

  • TSX Alpha Exchange (Canada): Introduced a randomized 1-3 millisecond delay on incoming orders
  • NYSE American: Proposed a 350-microsecond speed bump but withdrew the plan after regulatory pushback
  • Cboe EDGA: Implemented a liquidity provider protection delay
  • London Stock Exchange: Explored a speed bump for its SETS order book
  • Eurex: Uses a passive liquidity protection delay in certain products Each implementation balances the trade-off between protecting liquidity providers and maintaining fair access for all market participants.
SPEED BUMP MECHANICS

Frequently Asked Questions

Explore the technical and regulatory nuances of intentional latency mechanisms designed to level the playing field in fragmented electronic markets.

A speed bump is an intentional, asymmetric microsecond delay introduced by a trading venue's matching engine to neutralize the speed advantage of high-frequency traders. Unlike natural network latency, this is a deliberate pause—typically between 350 microseconds and 3 milliseconds—applied only to aggressive, liquidity-taking orders. The mechanism works by inserting a randomized or fixed delay into the order entry gateway before an incoming marketable order reaches the matching engine, while resting liquidity-providing orders remain unaffected. This temporal asymmetry prevents latency arbitrage strategies from picking off stale quotes before market makers can update their prices, effectively protecting resting liquidity providers from adverse selection.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.