Free-XOR optimization is a technique in garbled circuits that allows XOR gates to be evaluated without any cryptographic operations or associated ciphertexts, reducing computation and communication costs. The method works by having the circuit garbler choose a fixed, secret global offset R and setting the wire labels such that the label for 0 and the label for 1 on every wire differ by exactly this same value. This algebraic relationship means the output label of an XOR gate is simply the XOR of the two input labels, requiring no encryption, decryption, or garbled table transmission.
Glossary
Free-XOR Optimization

What is Free-XOR Optimization?
A foundational cryptographic technique that eliminates the need for encryption and ciphertext transmission when evaluating XOR gates within a garbled circuit protocol.
Introduced by Kolesnikov and Schneider, this optimization exploits the free-ness of XOR in the random oracle or correlation-robust hash model, making the evaluation of XOR gates computationally negligible. Since practical circuits are often heavily composed of XOR gates, Free-XOR dramatically reduces the overall bandwidth and CPU overhead of secure two-party computation protocols. It is a standard feature in modern frameworks like MP-SPDZ and Obliv-C, enabling efficient MPC-based inference for privacy-preserving machine learning.
Key Features of Free-XOR
Free-XOR is a foundational optimization in garbled circuits that eliminates cryptographic operations for XOR gates, dramatically reducing both computation and communication overhead in secure two-party computation.
Zero-Cost XOR Gates
The core insight of Free-XOR is that XOR gates require no ciphertexts and no cryptographic operations during evaluation. The garbler selects a global offset R (a random bit-string) and sets wire labels such that for any XOR gate with inputs A and B, the output label is simply A ⊕ B. The evaluator computes the output label by XORing the input labels they already possess, requiring only a single bitwise XOR operation rather than decrypting a garbled table. This eliminates the 4 ciphertexts per gate typically required in Yao's original construction.
Global Offset Technique
Free-XOR relies on a global offset R chosen uniformly at random by the garbler. For every wire w, the garbler assigns two labels: W⁰ (representing logical 0) and W¹ = W⁰ ⊕ R (representing logical 1). This invariant ensures that for any XOR gate with input wires x and y and output wire z, the relationship Z⁰ = X⁰ ⊕ Y⁰ holds, and the offset R remains consistent across the entire circuit. The evaluator never learns R, preserving security while enabling free evaluation.
AND Gate Cost Remains
While XOR gates become free, AND gates still require cryptographic operations. Each AND gate in a Free-XOR circuit requires the garbler to construct a garbled table of 3 ciphertexts (reduced from 4 using the row-reduction technique). The evaluator must decrypt exactly one of these ciphertexts using the input labels. This asymmetry motivates circuit designers to minimize the multiplicative depth and express logic using as many XOR gates as possible, transforming AND-heavy circuits into XOR-heavy equivalents where feasible.
Compatibility with Half-Gates
Free-XOR is fully compatible with the Half-Gates optimization (Zahur et al., Eurocrypt 2015), which reduces AND gate cost to 2 ciphertexts per gate. Together, these techniques form the backbone of modern efficient garbled circuit protocols. The combination yields a total communication cost of 2κ bits per AND gate (where κ is the computational security parameter) and 0 bits per XOR gate, making the protocol bandwidth nearly proportional to the number of AND gates in the circuit. This pairing is implemented in frameworks like EMP-toolkit and MP-SPDZ.
Security Assumption: Correlation Robustness
Free-XOR requires a stronger cryptographic assumption than standard garbled circuits. The construction relies on a correlation-robust hash function (or a random oracle) to mask the relationship between wire labels. Specifically, the hash function H must satisfy that H(W⁰, i) ⊕ H(W¹, i) is unpredictable even given W⁰ and W¹ = W⁰ ⊕ R. This property prevents the evaluator from learning the global offset R when decrypting AND gate ciphertexts. The assumption is strictly stronger than the dual-key cipher security used in non-Free-XOR constructions but is widely accepted as reasonable in practice.
Practical Impact on Secure Computation
Free-XOR transformed secure two-party computation from a theoretical curiosity into a practical tool. In typical circuits, XOR gates often constitute 30-70% of total gates, making the optimization substantial. For example, in AES evaluation (a common MPC benchmark), the S-box circuit contains approximately 56 XOR gates and 32 AND gates per round, meaning Free-XOR eliminates ciphertexts for over 60% of the gates. Combined with Oblivious Transfer Extension for input handling, Free-XOR enables secure evaluation of circuits with millions of gates in seconds rather than hours.
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Frequently Asked Questions
Clear answers to common questions about the Free-XOR technique in garbled circuits, its security assumptions, and its impact on secure multi-party computation performance.
The Free-XOR optimization is a seminal technique in garbled circuits that allows XOR gates to be evaluated without any cryptographic operations or associated ciphertexts, effectively making their computational and communication cost zero. It works by having the circuit garbler choose a global, random offset value (R) and then setting the wire labels such that for every wire w, the label representing 0 and the label representing 1 differ exactly by this offset: W1 = W0 ⊕ R. When an XOR gate with input wires A and B and output wire C is garbled, the output label is simply computed as the XOR of the two input labels: C0 = A0 ⊕ B0 and C1 = C0 ⊕ R. The evaluator can compute the correct output label by XORing the two input labels they hold, requiring no decryption, no garbled table, and no communication beyond the input labels themselves. This optimization, introduced by Kolesnikov and Schneider in 2008, fundamentally changed the cost profile of secure two-party computation, making XOR-heavy circuits like AES dramatically cheaper to evaluate privately.
Related Terms
Free-XOR is a foundational optimization within the garbled circuits protocol. Understanding these related primitives is essential for grasping how secure two-party and multi-party computation achieves practical performance.
Garbled Circuits
The foundational protocol, introduced by Andrew Yao, that enables two parties to jointly evaluate a boolean circuit over private inputs. One party (the garbler) encrypts the circuit, and the other (the evaluator) computes it using oblivious transfer for input keys. Free-XOR eliminates the cryptographic cost of XOR gates within this framework.
Oblivious Transfer (OT)
A fundamental primitive where a sender inputs two messages and a receiver inputs a choice bit. The receiver learns only their chosen message, and the sender learns nothing about the choice. In garbled circuits, OT is used to securely deliver the input wire labels to the evaluator without revealing the garbler's input mapping.
Point-and-Permute
A complementary optimization that prevents the evaluator from learning the semantic value of a wire. A random permutation bit is appended to each wire label, and the garbled truth table is sorted accordingly. This allows the evaluator to identify the correct decryption row without knowing if it corresponds to a logical 0 or 1, crucial for maintaining privacy alongside Free-XOR.
Half-Gates Optimization
An advanced technique that reduces the size of an AND gate to just two ciphertexts, down from the standard four. It cleverly combines two independent garbled AND gate constructions, each requiring only one ciphertext. When combined with Free-XOR, this makes garbled circuits highly bandwidth-efficient for complex functions.
Oblivious Transfer Extension
A protocol that efficiently extends a small number of computationally expensive base OTs (using public-key crypto) into a large number of OTs using only fast symmetric-key operations. This is critical because evaluating a garbled circuit requires an OT for every input bit of the evaluator, and OT extension makes this practical at scale.
AES-NI Hardware Acceleration
Modern CPUs provide native instructions for accelerating AES encryption and decryption. In the context of garbled circuits, the underlying cryptographic calls (often instantiated with a fixed-key AES cipher) are dramatically sped up by AES-NI, making the Free-XOR optimization—which relies on fast XORs of these cipher outputs—even more performant in practice.

About the author
Prasad Kumkar
CEO & MD, Inference Systems
Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.
His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.
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