Memory Access Obfuscation

Dynamically randomizes the physical memory addresses where tensors and weights are stored at each execution run. An attacker observing the bus sees a different address map every time, making static memory dumps useless. This is often combined with page table manipulation to create a non-deterministic mapping between virtual and physical addresses without breaking the model's computational graph.

Inserts spurious, non-functional memory read and write operations into the execution stream. These decoy accesses are indistinguishable from real ones to an external observer, flooding the memory bus with noise. Key implementation details include:

• Spatial dummies: Accessing unused memory regions
• Temporal dummies: Inserting idle cycles with fake transactions
• Statistical mimicry: Ensuring dummy traffic matches the distribution of real access patterns

Transforms the natural, operation-dependent memory access sequence into a uniform, repetitive pattern. Instead of revealing distinct phases (e.g., convolution bursts followed by pooling), the memory controller executes a fixed-stride, periodic access schedule. This removes the temporal side-channel that would otherwise allow an attacker to identify layer boundaries and infer the model architecture.

Prevents side-channel leakage through CPU performance monitoring units (PMUs). Sophisticated attackers can use cache hit/miss ratios and bus transaction counts to infer access patterns. This defense virtualizes or freezes performance counters during secure inference, reporting static, pre-programmed values that reveal nothing about the actual memory activity.

Adopts cryptographic ORAM protocols at the hardware level to provably hide access patterns. Every logical memory access is translated into multiple physical accesses to random locations, ensuring the observed sequence is computationally indistinguishable from random noise. While traditionally high-overhead, lightweight Path ORAM variants are now being optimized for embedded ML accelerators.

The on-the-fly encryption of data traveling between a processor and external memory. This ensures that an attacker physically probing the memory bus cannot capture plaintext model weights or inputs, even if they bypass memory access pattern obfuscation.

• AES-CTR and AES-XTS are common cipher modes used for low-latency bus encryption
• Often implemented in the memory controller to be transparent to the CPU
• Critical for protecting models deployed on edge devices with exposed DRAM interfaces

A class of defenses that eliminate or mask physical information leakage—including timing, power consumption, and electromagnetic emanations—from a processor running model inference. Memory access obfuscation specifically targets the address bus side-channel.

• Power analysis attacks can reveal operand values during multiply-accumulate operations
• Electromagnetic probes can reconstruct layer types by their distinct power signatures
• Mitigations include constant-weight coding and shielded enclosures

Specific countermeasures ensuring that the execution time of cryptographic operations or model inference is constant and independent of secret data. Without this, attackers can infer weight values from latency variations in memory fetches.

• Constant-time programming eliminates data-dependent branching
• Cache line locking prevents timing leaks from cache hits vs. misses
• Combined with memory access obfuscation, it closes both spatial and temporal side-channels

A hardware-enforced secure area within a main processor that guarantees the confidentiality and integrity of code and data loaded inside it. TEEs like ARM TrustZone and Intel SGX isolate model inference from the host operating system.

• Memory pages within the TEE are encrypted and integrity-checked by the memory encryption engine
• Provides a hardware root of trust that complements software-level memory access obfuscation
• Protects against a compromised OS attempting to snoop on model memory access patterns

The process of partitioning a neural network's computational graph and parameters across multiple isolated devices or secure enclaves so that no single node possesses the complete model. This raises the bar for memory bus analysis.

• An attacker must compromise multiple physical devices simultaneously to reconstruct the full model
• Shards can be distributed across geographically separated data centers
• Often combined with SMPC protocols for secure distributed inference

An active defense mechanism that immediately and irrevocably erases cryptographic keys, model weights, and sensitive data from memory upon detection of a physical tampering event. This is the last line of defense when memory access obfuscation is breached.

• Triggered by tamper switches, voltage anomalies, or enclosure breaches
• Must complete within nanoseconds to prevent data extraction via cold-boot attacks
• Commonly implemented in Hardware Security Modules (HSMs) and secure elements