Logic Locking

The foundational mechanism of logic locking involves inserting additional XOR or XNOR gates at strategic locations within the netlist. These key-gates act as programmable switches. When an incorrect key is applied, the key-gates invert the logic signal, causing the circuit to produce erroneous outputs. The correct secret key restores the original Boolean functionality, ensuring only authorized users can activate the chip. The placement of these gates is critical; poor placement can leave the design vulnerable to Boolean satisfiability (SAT) attacks.

Unlike combinational locking that modifies static logic gates, sequential locking embeds finite state machines (FSMs) into the design. The circuit must traverse a specific, hidden sequence of states—triggered by the correct key—before it enters functional mode. Incorrect keys trap the circuit in an obfuscated mode that produces meaningless outputs. This technique dramatically increases the time complexity for attackers because the key is not applied in parallel but distributed across multiple clock cycles, resisting traditional SAT-based attacks.

SFLL is a provably secure logic locking family designed to thwart SAT attacks. It works by intentionally corrupting the output behavior for a specific set of input patterns, effectively 'stripping' the original function. The correct key restores these corrupted outputs using a restoration unit. The key insight is that an attacker cannot distinguish between a wrong key that corrupts many outputs and the correct key that corrupts only the stripped set, making the SAT attack exponentially harder to resolve.

Logic locking serves as a powerful deterrent against hardware Trojan insertion, a malicious modification of a circuit during fabrication. By locking the design, an adversary at an untrusted foundry cannot identify the rare trigger conditions needed to activate a Trojan without knowing the key. The obfuscated netlist hides the true functional paths, making it computationally infeasible to insert a targeted Trojan that avoids detection during post-manufacturing testing.

The security of logic locking is only as strong as its key storage. Keys are typically stored in tamper-resistant non-volatile memory or derived from a Physically Unclonable Function (PUF). A PUF generates a unique, device-specific fingerprint from silicon manufacturing variations, eliminating the need to store a digital key. On-chip sensors monitor for physical tampering attempts, and a detected intrusion triggers zeroization, instantly erasing the key and rendering the chip permanently non-functional.

A critical metric for locking strength is the impact on logic cones—the set of gates that fan out to a primary output. Effective locking maximizes the number of outputs affected by a single wrong key bit, creating a 50% Hamming distance in output corruption. This ensures that even a single-bit error in the key causes widespread, unpredictable failure across the chip. Defensive analysis tools measure this output corruptibility to ensure the locking is not isolated to a single, easily bypassed logic cone.

A hardware security primitive that derives a unique, unclonable cryptographic key from the inherent microscopic manufacturing variations in a silicon chip. Rather than storing a key in memory—where it can be extracted—a PUF generates the key dynamically on power-up.

• Challenge-Response Pairs (CRPs): The PUF is queried with a challenge and produces a repeatable, device-specific response
• Key Generation: The PUF response is used to derive the secret key that unlocks the logic-locked circuit
• Tamper Evidence: Any physical probing alters the delicate analog characteristics, destroying the key

When combined with logic locking, a PUF ensures the unlocking key is intrinsic to the specific chip instance, making it impossible to clone the design onto a different piece of silicon.

The process of encrypting the configuration file (bitstream) that programs an FPGA with the implemented model architecture and weights. Without decryption, the bitstream is unintelligible.

• Symmetric Encryption: The bitstream is encrypted with AES-GCM or similar at design time
• On-Chip Decryption: A dedicated hardware decryptor inside the FPGA unwraps the bitstream during configuration
• Key Storage: The decryption key resides in battery-backed RAM or eFuses on the FPGA, separate from the bitstream storage

This prevents an attacker from intercepting the configuration data on the PCB traces or from cloning the FPGA's flash memory to replicate the model on an unauthorized device.

A class of defenses that eliminate or mask the physical information leakage from a processor running model inference. Attackers can extract keys or model weights by observing:

• Power Analysis: Fluctuations in current draw during cryptographic operations
• Electromagnetic Emanations: Radio-frequency signals emitted by switching transistors
• Timing Side-Channels: Variations in execution latency that correlate with secret data

Mitigations include constant-time algorithms, power balancing circuits, and shielding. For logic-locked chips, side-channel resistance prevents an attacker from extracting the secret key by simply measuring the device during the unlocking sequence.

A dedicated, tamper-resistant hardware chip designed to securely store cryptographic keys and execute sensitive operations in an isolated environment. It operates as a separate physical component from the main application processor.

• Secure Key Storage: Keys never leave the secure element in plaintext
• Isolated Execution: Decryption and authentication operations run inside the element's hardened boundary
• Tamper Detection: Active mesh sensors and environmental monitors trigger zeroization if physical intrusion is detected

In a logic-locking architecture, the secure element can serve as the trusted key vault that releases the unlocking key only after verifying the integrity of the host system through remote attestation.

A cryptographic protocol that allows a remote party to verify the integrity and trusted state of a device's software and hardware environment before provisioning a decryption key or allowing model execution.

• Measurement: The device computes a cryptographic hash of its firmware, OS, and runtime state
• Attestation Report: The measurement is signed by a trusted hardware root (e.g., TPM or TEE)
• Verification: The remote server validates the signature and compares the measurement against a known-good golden value

For logic-locked ICs deployed in the field, remote attestation ensures the chip is running authentic, untampered firmware before the unlocking sequence is initiated, preventing attackers from bypassing the lock by patching the runtime.

An active defense mechanism that immediately and irrevocably erases cryptographic keys, model weights, and sensitive data from memory upon detection of a physical tampering event.

• Tamper Sensors: Switches, light sensors, and mesh circuits detect enclosure opening or drilling
• Instant Response: On trigger, the system overwrites volatile memory and clears non-volatile key storage
• Power Glitch Detection: Monitors for abnormal power fluctuations indicative of fault injection attacks

Zeroization is the last line of defense in a logic-locked system. If an attacker attempts to physically extract the key or probe the unlocked circuit, the device self-destructs its secrets before they can be read, rendering the chip permanently non-functional.