Static Power (Leakage Power)

The primary source of static power is subthreshold leakage current. Even when a transistor's gate voltage is below its threshold (the 'off' state), a small current flows between its source and drain due to quantum mechanical effects. This current is exponentially dependent on the threshold voltage (Vt) and temperature. As transistor sizes shrink to nanometers, this leakage becomes a dominant factor in total power consumption, especially for chips with billions of transistors.

Static power is highly sensitive to temperature, increasing exponentially as the junction temperature of the silicon rises. This creates a thermal runaway risk: higher power consumption increases temperature, which in turn increases leakage current, leading to even higher power and temperature. Effective thermal management and dynamic thermal throttling are essential to control this positive feedback loop in densely packed AI accelerators.

Static power is profoundly affected by semiconductor manufacturing processes and operating voltage:

• Process Node: Leakage increases with each smaller technology node (e.g., from 28nm to 7nm) due to shorter channel lengths and thinner gate oxides.
• Supply Voltage (Vdd): Leakage current increases super-linearly with Vdd.
• Threshold Voltage (Vt): Using High-Vt transistors in non-critical paths reduces leakage but slows switching speed. Designers use multi-Vt libraries to strategically trade off speed and leakage.

The most effective circuit-level technique to eliminate static power is power gating. This involves using a header switch (PMOS) or footer switch (NMOS) to completely disconnect a logic block's power supply (Vdd) or ground (Vss). When gated off, leakage is reduced to near zero. This is crucial for AI accelerators, allowing unused cores or memory banks to be powered down between inference bursts. The trade-off is the energy and latency overhead of saving/restoring state when waking the block.

Static power is managed through a combination of design decisions and runtime techniques:

• Design-Time: Selection of process node, transistor Vt, and clock gating insertion (which reduces dynamic power but also eliminates switching activity that can mask leakage).
• Runtime: Activation of power gating, dynamic voltage scaling (DVS), and body biasing. Adaptive Body Biasing (ABB) dynamically adjusts the transistor's body voltage to alter its Vt, increasing Vt (reducing leakage) during idle periods and decreasing Vt (improving speed) during active computation.

Static power is the defining constraint for always-on sensing and wake-on-inference systems. These systems use a tiny, ultra-low-leakage microcontroller or microNPU to continuously monitor sensors. The total system milliwatt budget may be under 10mW, making static power the dominant drain. This necessitates the use of specialized low-leakage libraries, extensive power gating, and potentially near-threshold computing (NTC) for the always-on domain, while the high-performance AI core remains completely power-gated until activated.

Multi-Threshold CMOS (MTCMOS) is a design methodology that uses transistors with different threshold voltages (Vt) on the same chip. High-Vt transistors are used in the power gating switches because they have very low leakage when off, while low-Vt transistors are used in the core logic for high performance. This allows designers to optimize the trade-off between speed and static power. Libraries with multiple Vt cells are standard in modern synthesis flows, enabling automatic leakage optimization during place-and-route.

Body biasing (or back-gate biasing) dynamically adjusts the threshold voltage (Vt) of transistors by applying a voltage to the transistor body (well).

• Reverse Body Biasing (RBB): Increases Vt to drastically reduce subthreshold leakage during idle periods, at the cost of slower switching speed.
• Forward Body Biasing (FBB): Decreases Vt to increase performance during active computation. This technique requires a triple-well or silicon-on-insulator (SOI) process. Adaptive Body Biasing (ABB) systems dynamically control this bias based on workload and temperature.

Input Vector Control is a software/architectural technique that forces the inputs of an idle logic block into a state that minimizes the internal switching activity and creates the least leaky state for the underlying transistors. By placing combinational logic into a low-leakage state before entering a sleep mode, the overall static power of the block is reduced. This requires analysis to determine the minimum leakage vector (MLV) and control logic to apply it, often managed by the system's Power Management Unit (PMU).

Dynamic Voltage Scaling (DVS) and Dynamic Voltage and Frequency Scaling (DVFS) primarily target dynamic power (∝ V²), but they also significantly impact static power. Leakage current has an exponential relationship with supply voltage (VDD). By lowering VDD for reduced performance states, subthreshold leakage is dramatically reduced. DVFS is a cornerstone of system-level power management, allowing the operating point (voltage/frequency) to be scaled to the minimum required for the workload, thereby reducing all components of power consumption.

Leakage power has a super-linear relationship with junction temperature. As temperature increases, leakage currents rise exponentially. Therefore, effective thermal management is a critical indirect technique for controlling static power.

• Dynamic Thermal Management (DTM): Techniques like thermal throttling reduce frequency/voltage to lower temperature and thus leakage.
• Packaging & Cooling: Improved heat sinks and system design maintain lower operating temperatures. For always-on components, even a few degrees reduction can yield significant leakage savings over the device lifetime.

Dynamic power is the electrical power consumed by a digital circuit due to the charging and discharging of capacitive loads during logic transitions. It is the dominant power component during active computation. Its consumption is governed by the formula: P_dynamic = α * C * V² * f, where:

• α is the activity factor (fraction of gates switching).
• C is the load capacitance.
• V is the supply voltage.
• f is the clock frequency. Unlike static power, dynamic power is only consumed when the circuit is actively switching. Reducing voltage (voltage scaling) has a quadratic effect on reducing dynamic power, making it a primary target for optimization in high-performance compute phases.

Power gating is a circuit-level technique that completely shuts off power to inactive or idle blocks of a silicon chip using a header or footer switch. This action:

• Eliminates both dynamic and static (leakage) power in the gated region.
• Introduces a time and energy penalty for turning the block back on (wake-up latency).
• Requires state retention strategies (e.g., retention flip-flops) for critical data. It is a coarse-grained, highly effective method for managing leakage power, especially in systems-on-chip (SoCs) where large blocks like an AI accelerator can be powered down between inference bursts.

Dynamic Voltage and Frequency Scaling (DVFS) is a real-time power management technique that adjusts a processor's operating voltage and clock frequency based on instantaneous computational workload. Its primary goals are:

• Minimizing dynamic power consumption, which scales with V² * f.
• Meeting performance deadlines with minimal energy. For AI inference, DVFS controllers can lower voltage/frequency during less compute-intensive model layers or when latency requirements are relaxed. It is a key software-hardware co-control mechanism for managing the energy-delay trade-off.

Thermal throttling is a protective, feedback-driven mechanism where a processor's operating frequency and voltage are automatically reduced when the die temperature exceeds a predefined safe threshold. This process:

• Prevents permanent silicon damage from overheating.
• Directly impacts inference performance and latency.
• Is often triggered by sustained high-power workloads, which are a sum of dynamic and static power dissipation. For always-on edge AI applications, managing thermal design power (TDP) is crucial to avoid throttling, which can cause unpredictable inference times.

Near-Threshold Computing (NTC) is a design paradigm where digital circuits operate with a supply voltage very close to the transistor's threshold voltage (V_th). This region offers a highly favorable trade-off between energy efficiency and performance for non-latency-critical tasks. Key characteristics include:

• Exponential reduction in static (leakage) power compared to super-threshold operation.
• A substantial, though sub-linear, reduction in dynamic power.
• Increased sensitivity to process, voltage, and temperature (PVT) variations, requiring specialized circuit design. NTC is explored for ultra-low-power always-on inference engines in sensor nodes.

Performance-per-watt is the fundamental efficiency metric for evaluating computing systems in power-constrained environments. It is defined as the amount of useful computational work delivered per watt of power consumed. For AI inference, this is commonly expressed as:

• Inferences per second per watt (inf/sec/W).
• Tera-operations per second per watt (TOPS/W) for hardware. This metric holistically captures the system-level impact of both dynamic power (from active compute) and static power (from leakage), guiding architectural choices, model compression, and hardware selection for edge deployment.