Duty Cycling

The duty cycle ratio is the primary metric, defined as the percentage of time a system is active within a total period. It is calculated as (Active Time / Total Period Time) * 100%. A 1% duty cycle means the system is active for 1ms every 100ms. This ratio directly determines the average power consumption, which scales linearly with it when static power is negligible. For example, a component drawing 100mA when active and 1µA when asleep with a 1% duty cycle has an average current of ~1mA.

The strategy is defined by two alternating states:

• Active Period (Ton): The short window where the system performs computation (e.g., running an inference), reads sensors, or transmits data. Power consumption is high.
• Sleep/Low-Power Period (Toff): The significantly longer window where non-essential circuitry is powered down or clock-gated. The system consumes only leakage power or the power required to maintain a wake-up timer. The key to efficiency is minimizing Ton (e.g., via model optimization) and maximizing Toff, while ensuring the active period is long enough to complete the required task.

Transitioning from sleep to active mode requires a wake-up source and incurs wake-up latency. Sources can be:

• Timer-based: A low-power oscillator triggers wake-ups at fixed intervals for periodic tasks.
• Event-driven: An external signal from a sensor, coprocessor, or communication module triggers an interrupt. The wake-up latency—the delay from the wake-up signal to the system being fully operational—is critical for applications with real-time constraints. Specialized low-power wake-up receivers are used to minimize this latency and energy cost.

Effective duty cycling requires intelligent scheduling that coordinates multiple tasks and hardware blocks. This involves:

• Burst Processing: Queuing sensor data during sleep and processing it in a single, consolidated active burst to avoid frequent, costly state transitions.
• Synchronization: Aligning the duty cycles of different subsystems (radio, sensor, CPU) so they wake up simultaneously, preventing one block from being idle while waiting for another.
• Dynamic Adjustment: Adapting the duty cycle ratio based on battery state of charge, task urgency, or environmental context to extend operational lifetime.

Implementing duty cycling involves navigating key engineering trade-offs:

• Latency vs. Energy: A lower duty cycle saves energy but increases response latency for event-driven tasks.
• Overhead Energy: The energy cost of the sleep/wake transition itself. If the active period is too short, this overhead can dominate, reducing net savings.
• State Retention: Determining what system state (e.g., model parameters in SRAM) must be preserved during sleep, which consumes retention power, versus what can be reloaded from flash on wake-up. These factors must be co-optimized with model compression techniques like quantization to minimize the required active time.

Duty cycling is essential for deploying machine learning on battery-powered edge devices. Common patterns include:

• Always-On Sensing: A tiny, ultra-low-power microcontroller unit (MCU) runs a simple keyword spotting or motion detection model continuously at a very high duty cycle (e.g., 99% sleep). Only upon detection does it wake the main AI accelerator (wake-on-inference).
• Periodic Inference: An environmental sensor node wakes every 10 minutes, captures data, runs a small image classification or anomaly detection model, transmits the result via LoRaWAN, and returns to sleep.
• Event-Triggered Pipelines: A vibration sensor triggers a full audio event classification pipeline only when an anomaly is detected, keeping the complex model powered down otherwise.

Effective duty cycling requires a hierarchical power architecture:

• Always-On Domain: A tiny, nano-power real-time clock (RTC) and wake-up controller manage the sleep timer and listen for external wake-on-inference events from simple coprocessors.
• Wake Sources: These trigger the active period and include:
  • Timer Interrupts (periodic scheduling).
  • GPIO Interrupts (from a PIR sensor, button press).
  • Analog Comparator (sensor threshold exceeded).
  • MicroNPU Interrupt (a simple binary classifier detecting an event). The main application processor and AI accelerator are only powered in the active state.

Dynamic Voltage and Frequency Scaling (DVFS) is a complementary hardware-level power management technique that dynamically adjusts a processor's operating voltage and clock frequency in response to real-time computational demand. It is often used in conjunction with duty cycling.

• Mechanism: The processor's voltage and frequency are scaled down during low-activity periods within an active duty cycle and ramped up for burst compute.
• Synergy with Duty Cycling: While duty cycling controls when the system is active, DVFS optimizes how the active system consumes power. Lowering voltage provides a quadratic reduction in dynamic power (P ~ CV²f).
• Example: A vision processor might run at 0.8V/500MHz for simple frame differencing but scale to 1.1V/1.5GHz when a duty cycle activates it for full object detection.

Power gating is a circuit-level technique that completely shuts off power to inactive functional blocks or cores on a silicon chip. It is the most aggressive form of power saving and a key enabler for deep sleep states in a duty cycle.

• Objective: Eliminates both dynamic power (from switching) and static power (leakage current), which becomes significant at advanced process nodes.
• Implementation: Uses header or footer switches (high-Vt transistors) to disconnect a block's power rail. Requires state retention registers or a full reboot upon wake-up.
• Duty Cycle Role: Defines the ultra-low-power 'off' state. The latency and energy cost of powering up a gated block is a critical parameter in determining the optimal duty cycle period.

Wake-on-inference is a hierarchical system architecture that enables ultra-efficient duty cycling by using a tiny, always-on classifier to gate the activation of a larger, more powerful model.

• Architecture: A low-power microcontroller or microNPU runs a minimal feature extractor and binary classifier (e.g., for sound event or simple motion detection). Only upon a positive detection does it trigger the main AI accelerator's duty cycle.
• Energy Impact: Dramatically reduces the duty cycle of the high-power accelerator, as it sleeps through irrelevant data. The always-on coprocessor typically consumes microwatts to milliwatts.
• Use Case: Smart speakers using a small keyword spotting model to wake the large automatic speech recognition system.

Joule per inference is the fundamental energy efficiency metric for evaluating duty cycling and other optimization techniques. It measures the total energy required to perform a single forward pass of a model.

• Calculation: Energy (Joules) = Average Power (Watts) × Inference Latency (Seconds). Duty cycling reduces the average power component over time.
• System-Level Metric: Accounts for all power domains: the AI accelerator, memory, sensors, and any always-on logic. A good duty cycling strategy minimizes Joules/inference without violating latency constraints.
• Trade-off Analysis: Used to compare the efficiency of different model architectures, hardware platforms, and power management policies like duty cycle timing.

A milliwatt budget is a strict system-level power constraint, often in the single or tens of milliwatts, that dictates the design of duty cycling and all other power management strategies for battery-operated or energy-harvesting devices.

• Design Driver: Imposes a hard limit on the average power consumption (P_avg). Given P_avg = (P_active * t_active + P_sleep * t_sleep) / Period, the duty cycle parameters (t_active, t_sleep, P_active, P_sleep) must be engineered to meet the budget.
• Consequence: Often necessitates extreme model compression, highly optimized sleep states (deep power gating), and sophisticated wake-up scheduling to stay within budget while delivering useful functionality.
• Typical Context: IoT sensor nodes, wearable health monitors, and environmental sensors powered by small batteries or energy harvesters.

Event-driven inference is an execution paradigm that tightly couples duty cycling with external stimuli. Instead of periodic wake-ups, the system's active duty cycle is triggered only by specific, predefined events from sensors or other subsystems.

• Contrast with Periodic Duty Cycling: Eliminates energy wasted on polling or waking up to find no relevant data. The 'sleep' period is indefinite until the event occurs.
• Implementation: Relies on ultra-low-power event detectors in the sensor or a dedicated wake-up controller. Examples include a pixel-change threshold in a vision sensor (event-based camera) or an amplitude threshold in an acoustic sensor.
• Optimal for Sparse Data: Maximizes energy efficiency in applications where interesting events are rare but require immediate, complex AI processing (e.g., wildlife monitoring, security, predictive maintenance).