Always-On Sensing

A dedicated, minimal microcontroller or hardware block that continuously samples and pre-processes data from one or more sensors (e.g., MEMS microphones, IMUs, ambient light sensors). Its core functions are:

• Sensor Fusion: Combining data from multiple low-rate sensors to detect context (e.g., device picked up, ambient light change).
• Wake-Up Logic: Running simple, deterministic algorithms (threshold checks, basic DSP) to filter noise and identify potential trigger events worthy of waking the next stage.
• Extreme Duty Cycling: Operating at kHz-range clock speeds and sub-milliwatt power levels, often leveraging subthreshold or near-threshold computing techniques.

A tiny, highly efficient neural processing unit or DSP core that executes the first stage of AI inference. This is the heart of the 'sensing' function.

• Runs a Minimal Model: Executes a heavily compressed model (e.g., for keyword spotting, simple audio event detection, or basic gesture recognition).
• Fixed-Function Pipeline: Often uses quantized (INT8/INT4) weights and activations, and may leverage sparse model formats for efficiency.
• Wake-on-Inference: Its primary output is a binary or low-confidence score decision. Only if this score exceeds a threshold does it trigger an interrupt to wake the main application processor or a larger AI accelerator.

The system is partitioned into independent power domains controlled by a Power Management Unit (PMU). This enables granular control:

• Always-On Domain: Contains the sensor hub, microNPU, real-time clock, and interrupt controller. This domain is never powered off.
• Switchable Domains: The main CPU, large NPU, memory, and peripherals reside in domains that can be completely power-gated when inactive.
• Clock Gating: Within active domains, clocks to idle sub-blocks are disabled to eliminate dynamic power waste.
• State Retention: Critical registers in powered-down domains may retain state using tiny amounts of leakage power to enable fast resume.

The software architecture is fundamentally interrupt-driven, not polled, to minimize CPU wake time.

• Interrupt Service Routine (ISR): A tiny, optimized handler on the always-on core that services the 'wake' interrupt from the microNPU.
• Context Buffering: The sensor hub may buffer several seconds of raw sensor data, allowing the main processor to 'look back' at the event that triggered the wake-up.
• Duty-Cycled Main Inference: The awakened main processor runs a larger, more accurate verification model on the buffered data. If confirmed, it executes the full response; if not, it quickly powers down again.

Memory access is a major power consumer. Always-on systems use specialized memory configurations:

• Tightly-Coupled Memory (TCM): Small, low-latency SRAM blocks for the always-on core's code and data, avoiding power-hungry accesses to larger, slower main memory.
• Non-Volatile Memory (NVRAM): May be used for storing model weights and critical state to allow instant recovery from deep sleep without DRAM refresh power.
• Memory Power Gating: Unused banks of SRAM/DRAM are power-gated to eliminate static power drain.

Predictable timing is critical for meeting the milliwatt budget.

• Real-Time Clock (RTC): Provides a low-power timebase for scheduling periodic sensor sampling or system health checks.
• Deterministic Latency: The pipeline from sensor event to wake-up interrupt must have bounded, predictable latency to ensure responsive user experience.
• Battery-Aware Scheduling: The system may adapt its sensing sensitivity or duty cycle based on battery state of charge to prolong device lifetime.

A system architecture where a minimal, ultra-low-power always-on coprocessor (e.g., a microcontroller or microNPU) runs a small detection model (like a keyword spotter). This coprocessor monitors sensor streams and only activates the main, high-power AI accelerator when a specific inference trigger is detected. This prevents the primary processor from idling at high power, dramatically extending battery life.

• Key Component: A dedicated, power-optimized inference engine (often < 1 mW).
• Example: A smart speaker's voice assistant remains in a deep sleep state until the coprocessor detects the "Hey Google" or "Alexa" wake word.

A strict power consumption constraint, typically in the range of single-digit to tens of milliwatts, imposed on an edge device's sensing subsystem. This budget is derived from the total energy available from a small battery or energy harvester over the device's target operational lifetime. For always-on sensing, the entire pipeline—sensor, analog front-end, and inference processor—must operate within this budget.

• Design Driver: Dictates architectural choices, sensor sampling rates, and model complexity.
• Typical Target: 1-10 mW for consumer wearables and IoT sensors to enable months of battery life.

A fundamental power management strategy where a system alternates between short active periods (for sensing and computation) and long sleep periods. Instead of running continuously, the sensor and processor are powered on only at fixed intervals to sample data, perform inference, and then immediately return to a low-power sleep state. This reduces the average power consumption proportional to the duty cycle ratio.

• Calculation: Average Power = (Active Power * Active Time) / Total Period.
• Application: Used in environmental sensors (e.g., temperature sampled once per minute) and periodic activity recognition.

An execution paradigm where model inference is triggered only by specific, predefined external events, rather than running on a fixed schedule. This is more efficient than pure duty cycling when event timing is unpredictable. The trigger is often a simple, ultra-low-power analog circuit or digital comparator that monitors a sensor signal for a threshold crossing.

• Hardware Trigger: A window comparator can detect when an accelerometer signal exceeds a 'motion' threshold.
• Use Case: A security camera begins recording and running object detection only when a passive infrared (PIR) sensor detects heat movement.

Ultra-low-power circuit design techniques essential for the always-on coprocessors in sensing systems.

• Subthreshold Operation: Transistors are run at a gate voltage below their threshold voltage. This reduces switching energy by orders of magnitude but makes circuits extremely slow (kHz range). Suitable for simple, non-latency-critical state machines and sensor polling.
• Near-Threshold Computing (NTC): Circuits operate with a supply voltage close to the threshold voltage. It offers a superior energy-delay product, providing a better balance of moderate performance (MHz range) and high efficiency for running small neural network inference.

A dedicated hardware block or integrated circuit that is critical for implementing always-on sensing. The PMU is responsible for:

• Generating and regulating multiple supply voltages for different system components (sensor, always-on core, main CPU, memory).
• Sequencing power rails during startup and shutdown to prevent latch-up.
• Controlling power domains, enabling power gating to completely shut off unused blocks and clock gating to halt clocks to idle logic.
• Managing sleep states and wake-up sequences based on triggers from the always-on domain. An intelligent PMU is the hardware enforcer of the milliwatt budget.