Power Gating

Power gating is implemented using header switches (PMOS transistors) placed between the VDD supply and the block, or footer switches (NMOS transistors) placed between the block and VSS (ground).

• Header Switches: Control the power (VDD) rail. Typically larger due to lower hole mobility in PMOS, requiring more area.
• Footer Switches: Control the ground (VSS) rail. More area-efficient due to higher electron mobility in NMOS.

The choice affects area, wake-up latency, and noise characteristics. Modern designs often use a combination for finer control.

When a block is powered down, its outputs become floating, potentially causing large leakage currents in connected, active blocks. Isolation cells (or clamp cells) are mandatory logic gates inserted at the outputs of a powered-down domain.

• They drive a known, safe logic value (e.g., logic 0) to the always-on domain.
• Prevent crowbar current in downstream logic.
• Are themselves always powered and are a key part of the power intent specification (e.g., defined in UPF).

Simply cutting power loses all internal register states. State Retention Power Gating (SRPG) preserves critical flip-flop data during sleep mode.

• Uses special retention flip-flops with a separate, always-on power supply for the state element.
• Only the combinational logic and non-retention storage are powered off.
• Enables a fast, context-preserving wake-up, crucial for processor caches and control units. The retention supply has minimal leakage compared to the full block.

Turning a block on/off is not instantaneous. Wake-up latency is the time from asserting the power-on signal to the block being functionally ready. Sleep latency is the time to safely power down.

• Dominated by the time to charge/discharge the large virtual power rail capacitance through the high-resistance power switch.
• Directly impacts the minimum idle time for which power gating is beneficial (the break-even time).
• Requires careful sequencing: enable isolation, save state, then cut power (sleep); restore power, restore state, then disable isolation (wake-up).

The physical distribution and control granularity of power switches are key design parameters.

• Fine-Grained Power Gating: Many small switches distributed throughout the block. Offers faster, more localized control and reduces peak in-rush current but has higher area overhead and routing complexity.
• Coarse-Grained Power Gating: Fewer, larger switches at the block perimeter. Lower area overhead but slower wake-up and larger localized current spikes.
• Multi-Granularity Hierarchies: Modern NPUs use a hierarchy, e.g., coarse switches for large blocks (tensor cores) and fine switches within for execution units.

When a large block is powered on, the simultaneous charging of all internal capacitance causes a massive, instantaneous in-rush current spike.

• This spike can cause a voltage droop on the shared power grid, disrupting neighboring active circuits (power integrity issue).
• Managed by staggered wake-up: sequentially enabling banks of power switches with a controlled delay.
• Requires dedicated control logic in the Power Management Unit (PMU) to sequence the enable signals, trading wake-up time for current slew rate control.

Power gating uses header switches (PMOS transistors between VDD and the block) or footer switches (NMOS transistors between the block and GND) to create a virtual power rail. When the switch is open, the block is disconnected from the true power supply, eliminating both dynamic power (from switching) and static leakage power. The key challenge is managing the inrush current when power is restored and ensuring state retention if needed.

• Fine-Grained Power Gating (FGPG): Switches are integrated into standard cells, allowing power-down of individual logic gates. Offers granular control but high area overhead.
• Coarse-Grained Power Gating (CGPG): Larger switches control power to entire macro blocks or cores. More common, with lower area impact.
• State Retention Power Gating (SRPG): A critical variant where a small, always-on power island retains register states (using retention flip-flops) while the rest of the logic is powered off, enabling fast wake-up.

Power gating intent is specified using the Unified Power Format (UPF) or Common Power Format (CPF). This defines power domains, isolation cells, level shifters, and retention strategies. The EDA flow must verify:

• Power Domain Crossing: Signals crossing from a powered-off to a powered-on domain require isolation cells to prevent floating values.
• Level Shifting: Voltage differences between domains require level shifters.
• Power Sequencing: Correct order for turning switches on/off to avoid latch-up or corruption.

Benefits: Drastic reduction in leakage power, which dominates at advanced process nodes (e.g., <7nm). Essential for meeting Thermal Design Power (TDP) limits. Costs:

• Area Overhead: 3-10% for switch cells and routing.
• Performance Penalty: Voltage drop (IR) across the switch.
• Wake-up Latency: Time to restore power and re-establish stable voltage (microseconds to milliseconds).
• Rush Current: Requires careful sequencing to avoid supply noise.

Neural Processing Units exploit extreme parallelism with many identical processing elements (PEs). Power gating is applied at multiple levels:

• PE Clusters: Idle clusters during low-utilization phases of a neural network layer.
• On-Chip Memory Banks: SRAM blocks not actively accessed.
• Specialized Functional Units: (e.g., non-linear activation units) when not in use. This granular control is a key driver for NPU Performance per Watt, allowing them to maintain high peak throughput while minimizing idle power in edge and mobile deployments.

Power gating does not operate in isolation. It is coordinated with other power management techniques:

• Clock Gating: Applied first to halt activity; power gating follows after a determined idle period.
• Dynamic Voltage and Frequency Scaling (DVFS): Often, frequency is ramped down before power gating a block.
• Power-Aware Scheduling: The OS or runtime (e.g., via ACPI states) determines when blocks are idle long enough to justify the wake-up latency cost of power gating. This coordination is managed by the Power Management Unit (PMU).

Clock gating is a complementary power-saving technique that disables the clock signal to idle circuit blocks. While power gating removes voltage to eliminate static (leakage) power, clock gating prevents unnecessary transistor switching to reduce dynamic power. It is a finer-grained, faster-acting control often used in conjunction with power gating.

• Mechanism: Inserts a gate (e.g., an AND gate) in the clock distribution path.
• Impact: Reduces dynamic power (P = αCV²f) by setting the activity factor (α) to zero for idle blocks.
• Use Case: Frequently used for functional units within a core that are not in use for a few clock cycles.

Dynamic Voltage and Frequency Scaling (DVFS) is a runtime technique that adjusts a processor's operating voltage and clock frequency based on instantaneous workload demand. It optimizes energy efficiency by lowering both voltage (V) and frequency (f) during low-utilization periods, providing a quadratic reduction in dynamic power (P ∝ V²f).

• Relationship to Power Gating: DVFS reduces power for active blocks; power gating removes power for completely idle blocks. They are often used in a hierarchy.
• Control Knobs: Managed by the OS or firmware via ACPI P-States.
• Example: A mobile NPU might drop from 1.0 GHz at 0.9V to 500 MHz at 0.7V during light inference tasks.

State Retention Power Gating (SRPG) is an advanced form of power gating where the main power supply to a logic block is shut off, but a small, isolated retention supply remains active to preserve the state of critical registers (retention flip-flops). This allows for ultra-low leakage during idle while enabling a faster wake-up than a cold start.

• Key Benefit: Eliminates the latency and energy cost of saving/restoring state to external memory.
• Circuitry: Requires special retention flip-flops and isolation cells.
• Typical Use: Applied to processor cores or large SRAM blocks in an SoC during short sleep states.

Leakage power, also called static power, is the power dissipated by a transistor due to unwanted subthreshold and gate oxide current when it is in a nominally 'off' state. It is a dominant power concern in modern nanometer-scale CMOS processes.

• Primary Target of Power Gating: Power gating's main purpose is to eliminate leakage power in idle blocks by removing the supply voltage (Vdd).
• Dependence: Increases exponentially with higher temperature and with process technology scaling.
• Formula: Not easily captured by a simple equation like dynamic power, but modeled as I_leakage * Vdd.

A Power Management Unit (PMU) is a dedicated hardware controller, often a microcontroller or finite-state machine, that orchestrates all power management features on a chip. It sequences power domains, controls power gating switches, manages DVFS regulators, and handles sleep state transitions.

• Role: Implements the low-level firmware for power state transitions dictated by higher-level standards like ACPI or PSCI.
• Integration: Communicates with voltage regulators (VRMs, LDOs) and clock generators.
• Critical Function: Ensures safe, glitch-free power-up and power-down of gated domains.

The Unified Power Format (UPF) is an IEEE standard (1801) that provides a tool-independent, consistent language for specifying power intent throughout the electronic design automation (EDA) flow. It is essential for designing and verifying complex power-gated systems.

• What it Specifies: Defines power domains, power switches (for gating), isolation cells, level shifters, and retention strategies.
• Workflow: Allows designers to describe power architecture once and have it interpreted correctly by synthesis, placement, routing, and verification tools.
• Industry Standard: Critical for modern SoC design where dozens of power domains may exist.