Leakage Power

Leakage power arises from fundamental quantum mechanical effects in sub-threshold transistors. The primary mechanisms are:

• Subthreshold Leakage (I_sub): Current that flows between the source and drain when the transistor is nominally off, due to carriers diffusing across the potential barrier. This is the dominant source in modern CMOS.
• Gate Oxide Tunneling (I_g): Current that tunnels through the thin insulating gate oxide layer.
• Gate-Induced Drain Leakage (GIDL): Leakage at the drain junction enhanced by a high gate field.
• Reverse-Bias Junction Leakage (I_j): Minority carrier diffusion and generation in the reverse-biased drain and source junctions. Leakage increases exponentially with reductions in threshold voltage (V_th) and gate oxide thickness, and with increases in temperature.

Leakage current has a strong, super-linear relationship with junction temperature. For subthreshold leakage, the dependence is often modeled as increasing by a factor of 1.5x to 2x for every 10°C rise in temperature. This creates a positive thermal feedback loop: higher power dissipation increases temperature, which in turn increases leakage power, leading to further temperature rise—a phenomenon known as thermal runaway if not managed. This makes leakage a primary concern for thermal design power (TDP) calculations and dynamic thermal management systems.

As semiconductor processes scale to smaller nodes (e.g., from 28nm to 7nm and below), leakage power becomes a larger fraction of total chip power. While dynamic power reduces with lower capacitance (C) and voltage (V), leakage increases dramatically due to:

• Lower threshold voltages (V_th) to maintain performance.
• Thinner gate oxides, increasing gate tunneling current.
• Higher transistor density, increasing the total leakage paths per unit area. In advanced FinFET and GAAFET nodes, designers use techniques like multi-Vt libraries (using high-Vt cells for non-critical paths) and forward body biasing to control leakage while meeting performance targets.

Leakage is addressed architecturally and at the circuit design level through several key techniques:

• Power Gating: Using header/footer switches to completely disconnect a logic block from VDD or GND, eliminating leakage. Requires state retention (SRPG) for rapid wake-up.
• Multi-Threshold Voltage (Multi-Vt) Design: Using high-Vt transistors in non-timing-critical paths to reduce leakage, and low-Vt transistors only where needed for speed.
• Input Vector Control: Ensuring that when a block is idle, its inputs are set to a state that minimizes the internal stack effect and leakage paths.
• Body Biasing: Applying a reverse bias to the transistor body to increase V_th (reducing leakage) during idle periods, or forward bias to decrease V_th for higher performance when active. These techniques are specified using standards like Unified Power Format (UPF).

Operating systems and hardware power management units (PMUs) actively combat leakage during system operation:

• C-States (Idle States): Deeper idle states (e.g., C6) aggressively power-gate cores and large portions of the cache, trading wake-up latency for drastic leakage reduction.
• Dynamic Power Gating: Fine-grained, hardware-controlled gating of execution units and cache banks during short idle periods within a core's active state (C0).
• Temperature-Aware DVFS: Dynamic voltage and frequency scaling algorithms consider leakage's temperature dependence, potentially lowering voltage more aggressively at high temperatures to break the thermal feedback loop.
• Power-Aware Scheduling: Consolidating workloads onto fewer, fully active cores and placing others into deep idle states to minimize the total silicon area suffering from leakage.

Accurately characterizing and predicting leakage power is complex due to its sensitivity to multiple variables:

• Process Variation (PVT): Leakage can vary by orders of magnitude across different chips from the same wafer (process corner) and with voltage/temperature. Design must account for worst-case fast-corner, low-V, high-T scenarios.
• State Dependence: Leakage of a logic block depends on its internal logic state (input vector), making average-case analysis necessary.
• Aging Effects: Over time, Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) can shift threshold voltages, altering leakage characteristics.
• Tooling: Electronic Design Automation (EDA) tools use statistical leakage models and Monte Carlo simulations to estimate leakage power during the design phase, but post-silicon measurement is required for validation.

Power gating is the most direct technique for eliminating leakage power. It uses header switches (PMOS) or footer switches (NMOS) to completely disconnect a circuit block from the power supply (VDD) or ground (VSS) when idle.

• Implementation: Controlled by the Power Management Unit (PMU) based on workload predictions.
• Trade-off: Introduces a wake-up latency and energy overhead for turning the power rail back on and restoring state.
• Advanced Form: State Retention Power Gating (SRPG) uses a separate, always-on voltage rail to preserve the contents of critical registers (e.g., flip-flops) while the main logic is powered down, enabling faster reactivation.

MTCMOS is a foundational design methodology that uses transistors with different threshold voltages (Vt) within the same circuit.

• High-Vt transistors are used in the sleep transistors for power gating switches. Their high threshold minimizes leakage current when they are off.
• Low-Vt transistors are used in the core logic paths. Their low threshold enables high switching speed and performance when the block is active.
• This creates a design optimized for both low static power (via high-Vt switches) and high dynamic performance (via low-Vt logic).

Body biasing dynamically adjusts the threshold voltage (Vt) of transistors by applying a voltage to the transistor body (well), separate from the source. This modulates leakage current.

• Reverse Body Biasing (RBB): Applying a voltage that increases the Vt. This reduces leakage power significantly during idle periods but also slows down the transistor.
• Forward Body Biasing (FBB): Applying a voltage that decreases the Vt. This boosts performance during active computation at the cost of higher leakage.
• Modern chips use Adaptive Body Biasing (ABB) to dynamically switch between RBB (for idle) and FBB (for active burst) modes.

While primarily targeting dynamic power (P ~ V²), scaling voltage has a profound secondary effect on leakage, which has an exponential relationship with voltage.

• Dynamic Voltage Scaling (DVS): The OS or PMU lowers the operating voltage (VDD) along with frequency during low-performance demand. This quadratically reduces dynamic power and exponentially reduces leakage.
• Adaptive Voltage Scaling (AVS): An advanced, closed-loop form of DVS. It uses on-die process monitors to measure actual silicon speed and adjusts voltage to the minimum required for a target frequency, eliminating the conservative voltage guardbands used in traditional DVS. This provides further leakage savings.

This software/compiler-aware technique forces a logic block into its lowest-leakage state before it is power-gated or put into a deep sleep state.

• Mechanism: The compiler or runtime determines the specific combination of input signals (the 'vector') that results in the maximum number of internal transistors being in a non-leaky 'off' state.
• Application: Applied when a hardware block (e.g., an NPU tensor core) is scheduled to be idle. The control logic applies this optimal vector, then triggers power gating.
• Benefit: Reduces the residual leakage in the brief period between functional idle and full power-down, and can lower the retention voltage needed for SRPG.

The effectiveness of power gating depends heavily on how the chip is divided into power domains.

• Fine-Grain Power Gating: Individual functional units (e.g., a single MAC array, a small SRAM bank) can be independently switched off. This enables precise, rapid power management but increases area overhead due to more switches and control logic.
• Coarse-Grain Power Gating: Large blocks or entire cores are switched as one unit. This has lower area overhead but suffers from slower wake-up and less granularity, potentially leaving active logic within a powered domain.
• Design Trade-off: Modern NPUs use a hierarchical approach, with coarse domains for major blocks and fine-grained gating within performance-critical units. This is specified using standards like the Unified Power Format (UPF).

Dynamic power is the power consumed by a digital circuit due to the charging and discharging of capacitive loads during logic transitions (switching activity). It is the dominant power component during active computation and is calculated by the formula: P_dynamic = α * C * V² * f.

• α (Activity Factor): The probability that a clock cycle results in a logic transition.
• C (Load Capacitance): The total capacitive load being switched.
• V (Supply Voltage): The operating voltage.
• f (Clock Frequency): The operating frequency.

Unlike leakage (static) power, dynamic power is only dissipated when the circuit is actively switching. Power management techniques like Dynamic Voltage and Frequency Scaling (DVFS) directly target dynamic power by reducing V and f.

Power gating is a circuit design technique used to eliminate leakage power by completely shutting off power to an idle functional block using header (PMOS) or footer (NMOS) switches. When a block is gated off, its leakage current drops to nearly zero.

• Header Switch: A high-Vt PMOS transistor placed between VDD and the power-gated block.
• Footer Switch: A high-Vt NMOS transistor placed between the block and GND.
• Isolation Cells: Required at the outputs of a powered-down block to prevent floating signals from causing crowbar current in connected active blocks.
• Retention Registers: Special flip-flops with a separate, always-on power supply used in State Retention Power Gating (SRPG) to preserve critical state during sleep.

This is the most effective method for combating leakage but incurs a power-up/down latency and energy penalty.

Dynamic Voltage and Frequency Scaling (DVFS) is a runtime power management technique that dynamically adjusts a processor's operating voltage and clock frequency in response to workload demands.

• Goal: To match computational capability to the required performance, minimizing energy consumption. Since dynamic power is proportional to V² * f, reducing both parameters yields super-linear power savings.
• Impact on Leakage: Lowering the supply voltage (V) also exponentially reduces subthreshold leakage current, providing significant static power savings. This makes DVFS a primary tool for managing total power (dynamic + leakage).
• ACPI P-States: Operating systems typically manage DVFS through ACPI-defined Performance States (P-states), each representing a specific voltage/frequency operating point.

Thermal Design Power (TDP) is a chip specification, expressed in watts, that represents the maximum amount of heat the cooling system is required to dissipate under a sustained, real-world workload. It is a crucial parameter for system thermal and mechanical design.

• Relationship to Power: TDP is not the maximum possible power consumption (which can be higher during short bursts), but a sustained power figure. The total power (P_total = P_dynamic + P_leakage) must be managed to stay within the TDP envelope under typical conditions.
• Leakage's Role: As transistor sizes shrink, leakage power constitutes a larger portion of TDP, especially at higher junction temperatures (leakage increases with temperature). Effective leakage management through power gating and DVFS is essential to stay within TDP limits.

Dark silicon refers to the significant fraction of transistors on a modern microprocessor or SoC that must remain powered off ('dark') at any given time due to thermal and power delivery constraints.

• Cause: The root cause is the utilization wall. While transistor density continues to increase (Moore's Law), the ability to supply power and remove heat has not kept pace. Activating all transistors simultaneously would cause instantaneous thermal failure.
• Leakage Connection: Even 'dark' silicon that is power-gated has near-zero leakage. However, the necessity of dark silicon is a direct consequence of the total power budget, of which leakage is a major, temperature-dependent component.
• Design Implication: Architects must design for heterogeneity and specialization, strategically activating only the most efficient hardware blocks (e.g., NPU, GPU, CPU) for a given task while keeping others dark.

Process-Voltage-Temperature (PVT) corners represent the extreme combinations of manufacturing variations and operating conditions used during chip design and sign-off to guarantee functionality, performance, and reliability.

• Process (P): Variations in transistor length (L), width (W), oxide thickness (Tox), and doping concentrations from the nominal manufacturing process. 'Fast' and 'Slow' corners model these extremes.
• Voltage (V): The range of supply voltage, including IR drop and noise.
• Temperature (T): The specified operating junction temperature range (e.g., -40°C to 125°C).

Critical for Leakage: Leakage current is highly sensitive to all three factors. Designers must analyze:

• Worst-Case Power (WCP): Often at the Fast process corner, High voltage, and High temperature (FHVTH) for maximum leakage.
• Worst-Case Performance (WCS): Often at the Slow process corner, Low voltage, and High temperature (SLVTH). Guardbands are added to voltage and timing to cover these corners, impacting energy efficiency.