Inferensys

Glossary

Asynchronous Execution

A programming model where launching a computational kernel does not block the host CPU, allowing computation and data transfer to overlap for improved NPU utilization.
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PERFORMANCE PROFILING AND AUTO-TUNING

What is Asynchronous Execution?

A core programming model for maximizing hardware accelerator utilization by decoupling task initiation from completion.

Asynchronous execution is a programming paradigm where the host CPU launches a computational task, such as an NPU kernel, and immediately continues its own execution without waiting for the task to complete. This non-blocking behavior enables the overlap of computation with data transfer and other operations, hiding latency and dramatically improving overall system throughput. On NPUs, this is typically managed through command queues and event-based synchronization.

This model is fundamental to achieving peak performance on parallel accelerators, as it allows the host to keep the NPU's compute units and memory buses continuously occupied. Effective use requires careful dependency management to avoid race conditions and is a primary target for auto-tuning systems that optimize queue depths and launch parameters. It directly contrasts with synchronous execution, where the host thread blocks until the launched operation finishes.

PERFORMANCE PROFILING AND AUTO-TUNING

Core Mechanisms & Implementation

Asynchronous execution decouples the host CPU from the accelerator, enabling overlapping computation and data transfer. This section details the core mechanisms, implementation patterns, and performance implications of this critical programming model for NPU acceleration.

01

Non-Blocking Kernel Launch

The fundamental mechanism where a computational kernel is enqueued for execution on the NPU without stalling the host CPU. The host receives a handle (e.g., a CUDA stream, a SYCL queue event, or a Metal command buffer) immediately, allowing it to proceed with other work.

  • Key Benefit: Eliminates CPU idle time while the NPU computes.
  • Implementation: Managed via vendor-specific APIs like cudaStream_t, sycl::queue::submit, or MTLCommandBuffer.
  • Consequence: Requires explicit synchronization later to ensure kernel completion before using results.
02

Streams and Command Queues

Logical execution channels that maintain the order of operations (kernels and memory transfers) submitted to the NPU. Multiple streams/queues can execute concurrently, enabling fine-grained task parallelism.

  • Function: Provide a sequence guarantee within a stream but allow out-of-order completion across different streams.
  • Use Case: Overlap data transfer for kernel B in Stream 1 with the execution of kernel A in Stream 0.
  • Hardware Support: Modern NPUs/GPUs have multiple hardware queues to service concurrent streams.
03

Overlap of Compute and Data Transfer

The primary performance goal of asynchronous execution. By using multiple streams, data transfer (Host-to-Device or Device-to-Host) for a subsequent operation can occur simultaneously with the kernel execution of a prior operation.

  • Pattern: Double-buffering or multi-buffering, where data is staged in pinned host memory.
  • Requirement: Requires pinned (page-locked) host memory for DMA transfers; standard malloc memory cannot be used for concurrent transfers.
  • Metric: Achievable throughput is often measured by how effectively this overlap hides PCIe or memory bus latency.
04

Explicit Synchronization Primitives

Mechanisms to coordinate between the host and device or between concurrent streams, ensuring data dependencies are respected.

  • Barriers (cudaStreamSynchronize, queue.wait()): Block the host thread until all preceding commands in a specified stream complete.
  • Events (cudaEvent_t, sycl::event): Can be recorded into a stream and later queried by the host or used to synchronize between streams via cudaStreamWaitEvent.
  • Implicit Synchronization: Certain operations, like a default-stream memory copy, cause a full device-wide barrier, breaking concurrency.
05

Dependency Management with Graphs

Advanced model where a workflow of kernels and memory operations is defined as a graph of nodes with explicit dependencies before launch. The runtime can then schedule the entire graph asynchronously and optimally.

  • Benefit: Reduces launch overhead and enables the driver to see the full workflow for advanced optimizations.
  • Representation: Nodes are operations (kernel, memcpy, memset); edges are dependencies.
  • Execution: The entire graph is launched as a single, asynchronous unit using APIs like CUDA Graphs or SYCL Graph.
06

Performance Impact and Profiling

Asynchronous execution transforms performance bottlenecks and profiling requirements.

  • New Bottleneck: Shifts focus from kernel runtime to pipeline latency and achieved concurrency. The goal is to keep all hardware units (compute engines, copy engines) busy.
  • Profiling Tools: Requires timeline visualizers (Nsight Systems, Intel VTune, ROCm rocprof) to see overlap, not just kernel timers.
  • Key Metrics: Kernel Occupancy (within a stream) and Engine Utilization (across all streams) become critical. Poor overlap often indicates insufficient stream parallelism or improper dependency management.
ASYNCHRONOUS EXECUTION

Performance Impact and Bottlenecks

This section details the asynchronous execution model, a core technique for maximizing hardware accelerator utilization by overlapping computation with data transfer and other host-side operations.

Asynchronous execution is a programming model where the launch of a computational kernel on an accelerator, such as a Neural Processing Unit (NPU), does not block the host CPU, allowing it to perform other tasks while the kernel runs. This decoupling enables the overlapping of data transfers between host and device memory with kernel computation, a technique known as hiding latency. By managing operations through non-blocking queues (e.g., CUDA streams, command queues), the system can achieve higher aggregate throughput and better utilization of both the accelerator and the host processor.

The primary performance benefit is mitigating the memory-bound or I/O-bound bottlenecks inherent in accelerator programming. Without asynchronous execution, the host CPU idles during kernel execution and data transfers, creating serialization points. Effective use requires careful dependency management via events and barriers to ensure correctness. In complex pipelines, concurrent kernel execution and double-buffering techniques can be layered atop this model to further saturate the NPU's compute units and memory hierarchy, moving the bottleneck toward being purely compute-bound.

EXECUTION MODEL

Synchronous vs. Asynchronous Execution

A comparison of the fundamental programming models for launching computational work on an NPU, focusing on host-device interaction and resource utilization.

FeatureSynchronous ExecutionAsynchronous Execution

Host Blocking

Kernel Launch Overhead

< 1 µs

< 1 µs

Data Transfer Overlap

Concurrent Kernel Execution

Host CPU Utilization During Kernel Run

0% (Blocked)

95-100%

Default Behavior in Vendor SDKs

Required Explicit Synchronization

Typical Use Case

Debugging, Simple Workflows

Production Pipelines, Latency Hiding

ASYNCHRONOUS EXECUTION

Common Use Cases and Patterns

Asynchronous execution is a foundational pattern for maximizing hardware utilization. These cards detail its primary applications and implementation strategies for NPU acceleration.

01

Overlap Compute with Data Transfer

The canonical use case for asynchronous execution is to overlap computation on the NPU with data transfer between the host CPU and the NPU's memory. This hides the latency of PCIe or on-chip fabric transfers.

  • Pattern: Launch an asynchronous memory copy (e.g., H2D), then immediately launch a compute kernel that operates on previously transferred data, while the copy proceeds in parallel.
  • Benefit: Eliminates the memory-bound idle time of the NPU, moving the system toward being compute-bound.
  • Implementation: Requires the use of non-default streams and pinned (page-locked) host memory to enable true concurrency.
02

Concurrent Kernel Execution

Modern NPUs can execute multiple independent kernels concurrently across different streaming multiprocessors (SMs) or compute units. Asynchronous execution via separate streams enables this parallelism.

  • Use Case: Running a pre-processing kernel (e.g., normalization) alongside a main inference kernel on different data batches.
  • Requirement: Kernels must be resource-independent (not competing for the same hardware registers or shared memory per SM) to avoid resource contention and serialization.
  • Tooling: A kernel profiler (like Nsight Compute or vendor tools) is essential to verify true concurrency and identify serialization points.
03

Pipeline Parallelism for Batched Inference

Asynchronous execution enables the construction of software pipelines for high-throughput batched inference. The pipeline stages (e.g., copy, compute, copy-back) operate on different data batches simultaneously.

  • Pattern: Use multiple streams. While Stream 1 executes the kernel for Batch N, Stream 2 copies results for Batch N-1 back to host, and Stream 3 copies input for Batch N+1 to the NPU.
  • Metric: Maximizes aggregate compute throughput (e.g., inferences per second) by keeping all hardware units busy.
  • Auto-Tuning Link: The optimal number of concurrent batches and stream count is a key target for auto-tuning systems.
04

Integration with Host-Side Processing

Asynchronous execution allows the host CPU to perform auxiliary tasks—like preparing the next batch of data, running control logic, or handling I/O—without blocking the NPU.

  • Pattern: After launching an asynchronous kernel, the host thread is free to execute its own code. It later synchronizes (e.g., with streamSynchronize) to harvest results.
  • Benefit: Enables efficient heterogeneous computing where the CPU and NPU work in tandem on different aspects of a problem.
  • Caution: Requires careful synchronization to avoid data races where the host reads data before the NPU has finished writing it.
05

Dynamic Kernel Launch & Auto-Tuning

Asynchronous execution is critical for online auto-tuning systems where the performance of multiple kernel variants must be evaluated rapidly.

  • Pattern: An auto-tuner (e.g., a Kernel Tuner framework) can launch hundreds of kernel configurations asynchronously across different streams to profile them, using the NPU's performance counters.
  • Method: Techniques like Bayesian Optimization rely on launching candidate kernels asynchronously to gather performance data for the next iteration of the search.
  • Outcome: Dramatically reduces the total time required to search a large configuration space for optimal parameters like workgroup size or tile size.
06

Event-Based Synchronization & Dependencies

Advanced asynchronous workflows use events to create fine-grained dependencies between operations across different streams, enabling complex execution graphs.

  • Pattern: Record an event after a memory copy in Stream A. A kernel launch in Stream B can then wait for that event, ensuring data is ready before computation begins, without full stream synchronization.
  • Use Case: Essential for graphs with data dependencies where kernels consume outputs from other kernels running in different streams.
  • Framework Support: Low-level APIs (like CUDA/OpenCL events) and higher-level graph APIs (like CUDA Graphs) build on this primitive to define and launch pre-defined asynchronous workflows efficiently.
ASYNCHRONOUS EXECUTION

Frequently Asked Questions

A programming model where the launch of a computational kernel does not block the host CPU, allowing for overlapping computation and data transfer to improve NPU utilization.

Asynchronous execution is a programming model for hardware accelerators where the host CPU submits a computational task (a kernel) to the NPU and continues its own execution without waiting for the task to complete. This decoupling allows the host to prepare the next task while the NPU is still processing the current one, enabling concurrent operation between the CPU and the accelerator. The fundamental mechanism is the use of a non-blocking launch command, which returns control to the host immediately after placing the kernel in the NPU's command queue. The host can later synchronize with the NPU using explicit wait or event-based mechanisms to ensure results are ready before being used.

In the context of NPU acceleration, this model is critical for hiding the latency of kernel execution and data transfers, maximizing the overall system throughput. It transforms a sequential workflow (CPU prepare -> NPU compute -> CPU process results) into a pipelined one, where these stages can overlap.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.