Inferensys

Glossary

Roofline Model

The Roofline Model is an analytical performance model that visualizes the attainable performance of a computational kernel as a function of its operational intensity, bounded by hardware peak compute and memory bandwidth.
ML engineer working on model compression and quantization, laptop showing performance benchmarks, technical workspace.
PERFORMANCE ANALYSIS

What is the Roofline Model?

A visual performance model for analyzing computational kernels on hardware accelerators.

The Roofline Model is an analytical performance model that visualizes the attainable performance of a computational kernel as a function of its operational intensity, bounded by the hardware's peak compute throughput (FLOP/s) and memory bandwidth (bytes/s). It plots performance (y-axis) against operational intensity (x-axis) on a log-log scale, creating a characteristic 'roofline' shape. Kernels are plotted as points, instantly revealing whether they are compute-bound (limited by FLOP/s) or memory-bound (limited by memory bandwidth).

The model's primary value is in guiding hardware-aware optimization. For a memory-bound kernel, the goal is to increase operational intensity via techniques like loop tiling or kernel fusion to reuse data in caches. For a compute-bound kernel, optimization focuses on maximizing FLOP/s utilization through vectorization or mixed-precision computation. It is a foundational tool for performance architects and compiler engineers targeting NPUs, GPUs, and other accelerators, providing a clear, quantitative target for optimization efforts.

PERFORMANCE ANALYSIS

Key Components of the Roofline Model

The Roofline Model is a visual performance bound defined by two fundamental hardware limits. Understanding its components is essential for diagnosing bottlenecks and optimizing kernels for NPUs and other accelerators.

01

Operational Intensity

Operational Intensity is the primary independent variable in the Roofline Model. It is defined as the number of Floating-Point Operations (FLOPs) performed per byte of data transferred between the processor and the main memory hierarchy. It is measured in FLOPs/Byte.

  • High Intensity (>10-100 FLOPs/Byte): Kernels like dense matrix multiplication are compute-bound, limited by the chip's peak FLOP/s.
  • Low Intensity (<1 FLOP/Byte): Kernels like element-wise addition are memory-bound, limited by the system's memory bandwidth.

Calculating a kernel's operational intensity requires analyzing its algorithm to count total FLOPs and the minimum bytes that must be moved from DRAM.

02

Peak Compute Performance

Peak Compute Performance is the theoretical maximum number of floating-point operations a processor can perform per second, measured in FLOP/s (e.g., TeraFLOP/s or TFLOPS). This forms the horizontal 'roof' of the model.

  • This limit is determined by hardware specs: clock frequency, number of cores/ALUs, and SIMD width.
  • It is often specified for different numerical precisions (e.g., FP32, FP16, INT8). A modern NPU might have a much higher peak for INT8 than for FP32.
  • A kernel's performance cannot exceed this ceiling. If a kernel's operational intensity is high enough that its attainable performance plateaus at this line, it is compute-bound.
03

Peak Memory Bandwidth

Peak Memory Bandwidth is the theoretical maximum rate at which data can be transferred between the processor and its main memory (e.g., HBM, LPDDR), measured in Bytes/s (e.g., GB/s). This forms the diagonal 'slope' of the model.

  • This limit is determined by the memory bus width, data rate, and number of memory channels.
  • The slope of the roofline is defined as: Attainable GFLOP/s = (Bandwidth in GB/s) * (Operational Intensity in FLOP/Byte).
  • A kernel's performance cannot exceed this slope. If a kernel's performance falls along this line, it is memory-bound; every increase in operational intensity directly increases performance.
04

Attainable Performance Region

The Attainable Performance Region is the space below both the horizontal compute roof and the diagonal bandwidth slope. Any real computational kernel will plot as a point within this region.

  • Location Diagnoses Bottleneck: A point near the diagonal slope indicates a memory-bound kernel. Optimization should focus on improving data reuse (e.g., via tiling), reducing transfers, or increasing operational intensity.
  • A point near the horizontal roof indicates a compute-bound kernel. Optimization should focus on improving instruction-level parallelism, using vector/SIMD instructions, or leveraging specialized functional units (e.g., tensor cores).
  • The distance from the roof indicates the optimization headroom available for that kernel on that hardware.
05

Kernel Roofline & Optimization Target

A Kernel Roofline plot places a specific kernel's measured performance (in GFLOP/s) against its calculated operational intensity. This reveals its precise bottleneck.

  • Optimization Vector: The vertical distance from the kernel's point to the roofline represents lost performance. The goal is to move the point vertically upward.
  • Moving the Point: To improve a memory-bound kernel, you must increase its operational intensity (moving it rightward) via algorithmic changes like loop tiling, kernel fusion, or using cache-friendly data layouts. This moves it up the slope.
  • For a compute-bound kernel, you must improve the kernel's computational efficiency to utilize more of the hardware's peak FLOP/s, moving the point vertically upward against the roof.
06

Hierarchical (Multi-Ceiling) Roofline

The Hierarchical Roofline Model extends the basic model by adding multiple 'ceilings' that represent the performance limits of different levels of the memory hierarchy (e.g., L1 cache, L2 cache, HBM).

  • Each memory level has its own bandwidth and associated roof slope.
  • A kernel's operational intensity can be recalculated for data sourced from each cache level, showing which level is the current bottleneck.
  • This is critical for NPU optimization, where managing data movement between global memory, shared memory/SRAM, and register files is paramount. The model guides optimizations like operator fusion (to keep data in fast memory) and explicit memory hierarchy management.
PERFORMANCE MODELING

How to Use the Roofline Model for Analysis

The Roofline Model is a visual performance analysis tool that reveals the fundamental hardware limits of a computational kernel.

The Roofline Model is an analytical performance model that visualizes the attainable performance of a computational kernel as a function of its operational intensity. It plots performance (FLOPS/sec) against operational intensity (Ops/Byte) on a log-log scale. The model establishes two fundamental hardware ceilings: a memory bandwidth roof for data-bound kernels and a peak compute roof for compute-bound kernels. A kernel's performance is bounded by the lower of these two limits, forming the characteristic 'roofline' shape that gives the model its name.

To use the model, first profile your kernel to measure its actual arithmetic intensity and achieved performance. Plot this point on the roofline chart. If the point lies well below the roofline, the kernel is inefficient and optimization is possible. If it is near the memory-bound slope, focus on improving data reuse and access patterns. If it is near the flat compute roof, the kernel is compute-bound; consider algorithmic changes or leveraging hardware-specific intrinsics. The model is essential for hardware-aware optimization, guiding efforts toward the most impactful bottlenecks for NPUs and other accelerators.

ROOFLINE MODEL ANALYSIS

Compute-Bound vs. Memory-Bound: A Comparison

This table compares the defining characteristics, symptoms, and optimization strategies for computational kernels classified as compute-bound or memory-bound under the Roofline Model.

CharacteristicCompute-Bound KernelMemory-Bound Kernel

Primary Limiting Factor

Peak FLOP/s of the processor

Peak memory bandwidth (GB/s)

Operational Intensity

High (> Arithmetic Intensity threshold)

Low (< Arithmetic Intensity threshold)

Performance Ceiling

Attainable GFLOP/s = Peak GFLOP/s

Attainable GFLOP/s = (Bandwidth) * (Operational Intensity)

Typical Bottleneck

Floating-point units (ALUs)

Memory bus or cache hierarchy

Key Optimization Goal

Increase instruction-level parallelism (ILP), utilize vector/SIMD units

Improve data locality, maximize cache reuse, reduce memory transfers

Common Symptoms

High ALU utilization, low memory bandwidth usage

High memory bandwidth usage, low ALU utilization, frequent cache misses

Example Kernels

Dense matrix multiplication (GEMM), large convolutions

Element-wise operations, sparse matrix-vector multiply, data gathering

Beneficial Techniques

Loop unrolling, kernel fusion, mixed-precision arithmetic

Loop tiling, prefetching, memory coalescing, data layout transformations

HARDWARE-AWARE MODEL OPTIMIZATION

Practical Applications and Examples

The Roofline Model is a foundational tool for performance analysis, used to diagnose bottlenecks and guide optimization strategies for computational kernels on specific hardware. Its primary applications are in high-performance computing (HPC), machine learning, and hardware design.

01

Diagnosing Compute vs. Memory Bounds

The Roofline Model's primary use is to classify a kernel's performance limit. A kernel plotted below the roofline is memory-bound: its performance is limited by the speed of data movement from memory. A kernel plotted at the roofline is compute-bound: its performance is limited by the hardware's peak arithmetic throughput.

  • Example: A dense matrix multiplication with high operational intensity will likely be compute-bound on a GPU. A sparse matrix-vector multiplication with low operational intensity will be memory-bound.
  • Actionable Insight: For a memory-bound kernel, optimize data reuse, improve cache locality, or use compression. For a compute-bound kernel, maximize instruction-level parallelism or use lower precision (e.g., FP16).
02

Guiding Hardware-Aware Algorithm Design

Algorithm designers use the Roofline Model during early development to ensure new methods are suited to target hardware. By estimating a new algorithm's operational intensity, developers can predict its performance ceiling before implementation.

  • Real-World Case: When designing the Flash Attention algorithm, its creators analyzed the standard attention mechanism's low operational intensity (making it memory-bound). Flash Attention was explicitly designed to increase operational intensity by recomputing on-chip, moving its performance plot closer to the compute roof.
  • Use in NAS: Hardware-Aware Neural Architecture Search (NAS) can use roofline-derived metrics (attainable GFLOP/s) as a proxy for latency when evaluating candidate model architectures.
03

Optimizing for Specific NPU/GPU Architectures

Each accelerator has a unique roofline defined by its peak FLOP/s and memory bandwidth. Optimizing a kernel for an NVIDIA A100 is different than for a Google TPU v4 or an Apple Neural Engine. The model forces explicit consideration of these hardware ceilings.

  • Example Workflow:
    1. Profile a convolution kernel on the target NPU to get its achieved GFLOP/s.
    2. Calculate its operational intensity (FLOPs/byte).
    3. Plot it on the NPU's roofline chart.
    4. If memory-bound, apply NPU-specific optimizations like operator fusion to reduce DRAM traffic or utilize specialized on-chip memory (e.g., shared memory/SRAM).
04

Informing Hardware Procurement and Design

System architects and hardware designers use the Roofline Model for comparative analysis and target setting.

  • Procurement: Comparing the rooflines of different accelerators (e.g., GPU vs. TPU) for a specific workload profile (e.g., low-intensity recommendation models vs. high-intensity LLM training).
  • Hardware Design: Chip designers set targets for balance (FLOP/s per byte/s). A design with extremely high FLOP/s but low bandwidth will only benefit a narrow set of compute-intensive kernels. The model visualizes this trade-off.
  • Historical Example: The shift from CPUs to GPUs for AI was fundamentally a move to a hardware roofline with a much higher compute ceiling and a different balance point.
05

Analyzing Multi-Core and NUMA Systems

The basic roofline model can be extended to hierarchical systems. A multi-roofline model can depict different performance limits for different levels of the memory hierarchy (e.g., L1 cache, L2 cache, HBM).

  • NUMA Systems: On Non-Uniform Memory Access systems, different rooflines can be drawn for local vs. remote memory access. This highlights the severe performance penalty of not managing NUMA affinity.
  • Practical Use: Guides data placement and thread pinning strategies to ensure kernels access local memory, keeping them on the higher, local-memory roofline.
06

Quantifying the Impact of Precision Reduction

Changing numerical precision (e.g., FP32 → FP16 → INT8) directly alters both axes of the Roofline Model.

  • Operational Intensity (X-axis): Lower precision (INT8) means each byte transferred from memory represents more operations, effectively shifting the kernel's plot point to the right.
  • Peak Compute (Y-axis): Hardware can typically execute many more low-precision operations per second, raising the compute roofline.
  • Result: A kernel that is memory-bound in FP32 may become compute-bound in INT8, unlocking higher performance. This provides a quantitative framework for evaluating Post-Training Quantization (PTQ) and Quantization-Aware Training (QAT) benefits.
ROOFLINE MODEL

Frequently Asked Questions

A performance analysis tool for understanding the fundamental limits of computational kernels on specific hardware.

The Roofline Model is an analytical performance model that visualizes the attainable performance of a computational kernel or algorithm as a function of its operational intensity, bounded by the peak compute throughput and memory bandwidth of the hardware. It provides a two-dimensional plot where performance (in FLOPS/sec) is on the y-axis and operational intensity (in FLOPs/byte) is on the x-axis. The model establishes a 'roofline' that represents the absolute performance limit for any kernel on that hardware, determined by either the peak computational capability (compute-bound) or the memory bandwidth (memory-bound). This visual framework is essential for hardware-aware optimization, allowing developers to immediately identify whether an algorithm's performance is limited by arithmetic units or data movement and to quantify the potential headroom for improvement.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.