Inferensys

Glossary

FlashAttention

An IO-aware exact attention algorithm that dramatically speeds up and reduces the memory footprint of the self-attention mechanism, making it feasible to pre-train models on very long legal documents.
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IO-AWARE EXACT ATTENTION

What is FlashAttention?

An algorithm that accelerates the self-attention mechanism by minimizing reads and writes between GPU high-bandwidth memory and on-chip SRAM.

FlashAttention is an IO-aware exact attention algorithm that computes the standard self-attention output without approximation while dramatically reducing the number of memory reads and writes to GPU high-bandwidth memory (HBM). By fusing operations into a single CUDA kernel and tiling the computation to keep intermediate matrices in fast on-chip SRAM, it achieves significant speedups and reduces the memory footprint from quadratic to linear in sequence length.

This innovation is critical for domain-specific legal pre-training, where processing long documents like multi-page contracts and judicial opinions requires extended sequence lengths. By eliminating the memory bottleneck of traditional attention, FlashAttention enables the pre-training of legal language models on full documents rather than truncated chunks, preserving cross-paragraph context essential for accurate statutory interpretation and citation network analysis.

IO-AWARE EXACT ATTENTION

Key Features of FlashAttention

FlashAttention is an algorithm that computes exact self-attention with dramatically reduced memory reads/writes, making it feasible to pre-train models on very long legal documents.

01

IO-Awareness: Tiling the Computation

FlashAttention's core innovation is IO-awareness—it accounts for the speed hierarchy between GPU memory levels. Instead of materializing the full N×N attention matrix in slow High Bandwidth Memory (HBM), it:

  • Tiles the Q, K, and V matrices into blocks that fit in fast SRAM
  • Computes softmax attention incrementally within each block
  • Writes only the final output back to HBM

This reduces HBM reads/writes from O(N²) to O(N²/d), where d is the head dimension. For a 4K-token legal document, this can mean a 7.6x reduction in memory operations.

7.6x
Memory Access Reduction
02

Online Softmax with Rescaling

Traditional softmax requires two passes over the data: one to find the maximum value for numerical stability, and another to compute the exponential sum. FlashAttention fuses these into a single online softmax algorithm that:

  • Maintains running statistics (m, ℓ) as it iterates through blocks
  • Rescales previously computed partial sums when a new maximum is encountered
  • Produces mathematically identical output to the two-pass version

This is critical for legal models, where attention scores across long documents can have extreme dynamic ranges, and numerical precision directly impacts citation accuracy.

03

Recomputation Over Storage

In the backward pass, standard attention implementations store the full attention matrix from the forward pass, consuming O(N²) memory. FlashAttention recomputes attention scores on-the-fly during backpropagation:

  • Stores only the softmax normalization statistics (m, ℓ) from the forward pass
  • Recalculates QK^T values in SRAM during the backward pass
  • Trades a small increase in FLOPs for a massive reduction in memory footprint

This recomputation strategy enables training on 4-8x longer sequences than standard attention, directly enabling processing of full contracts and multi-page judicial opinions without truncation.

4-8x
Longer Sequence Training
04

FlashAttention-2: Parallelism and Work Partitioning

FlashAttention-2 improves upon the original by optimizing work partitioning across thread blocks and reducing non-matmul FLOPs:

  • Forward pass: Parallelizes over the sequence length dimension instead of batch and head dimensions, increasing occupancy
  • Backward pass: Parallelizes over the column dimension, eliminating the need for atomic adds and inter-thread communication
  • Reduces the number of non-matrix-multiply operations, which are disproportionately slow on modern GPUs

These optimizations yield a 2x speedup over FlashAttention-1, making long-document legal pre-training economically viable on existing GPU clusters.

2x
Speedup vs FlashAttention-1
05

FlashAttention-3: Hopper Architecture Exploitation

FlashAttention-3 targets NVIDIA's Hopper GPU architecture (H100) with three new techniques:

  • Warp-specialization: Dedicated warps for data movement (TMA) and computation, overlapping asynchronous loads with math
  • Ping-pong scheduling: Alternates between two sets of registers to hide memory latency
  • FP8 low-precision: Leverages Hopper's native FP8 tensor cores for attention computation, further reducing memory bandwidth

On H100 GPUs, FlashAttention-3 achieves 1.5-2.0x speedup over FlashAttention-2, reaching up to 740 TFLOPS—critical for training legal models on entire case law corpora within reasonable timeframes.

740 TFLOPS
Peak Throughput on H100
06

Memory Savings: Linear with Sequence Length

The memory footprint of standard attention scales quadratically with sequence length—a 16K-token legal document requires 256x more attention memory than a 1K-token passage. FlashAttention's memory scales linearly with sequence length:

  • Standard Attention: O(N²) memory for the attention matrix
  • FlashAttention: O(N) memory for the output and statistics
  • Enables processing of 64K+ token sequences on a single GPU

This linear scaling is the key enabler for domain-adaptive pre-training on full legal documents. Without it, models must truncate or chunk documents, breaking cross-reference reasoning between distant sections of a contract or opinion.

O(N)
Memory Complexity
FLASHATTENTION EXPLAINED

Frequently Asked Questions

Clear, technically precise answers to the most common questions about the IO-aware exact attention algorithm that is revolutionizing long-context legal AI.

FlashAttention is an IO-aware exact attention algorithm that computes the standard self-attention operation with significantly reduced memory reads and writes between GPU High Bandwidth Memory (HBM) and on-chip SRAM. It works by tiling the attention matrix computation into smaller blocks that fit entirely in SRAM, performing the softmax reduction incrementally without ever materializing the full N×N attention matrix in HBM. The algorithm uses a numerically stable online softmax technique and a custom CUDA kernel to fuse operations, achieving a 2-4x wall-clock speedup and reducing memory complexity from O(N²) to O(N) for sequence length N. This makes it feasible to train transformers on very long legal documents without approximation or sparsity.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.