Inferensys

Glossary

Fusion Planner

A fusion planner is a compiler component that constructs an optimal or near-optimal plan for which operator groups to fuse, often by exploring a search space of possible fusions using a cost model.
Developer reviewing semantic search engine results on laptop, relevance scores visible, technical search demo.
COMPILER COMPONENT

What is a Fusion Planner?

A fusion planner is the compiler subsystem responsible for determining the optimal grouping of operators to combine into single, efficient computational kernels.

A fusion planner is a compiler component that constructs an optimal or near-optimal plan for which operator groups to fuse, often by exploring a search space of possible fusions using a cost model. It operates on a computational graph, analyzing data dependencies and hardware characteristics to decide fusion profitability. The goal is to maximize performance by minimizing kernel launch overhead and improving data locality, while avoiding negative effects like increased register pressure.

The planner's decisions are guided by fusion heuristics and predictive models that estimate execution time and memory usage for candidate fused kernels. It must balance strategies like vertical fusion (chaining dependent ops) and horizontal fusion (combining parallel ops). Advanced planners in compilers like XLA, TVM, and MLIR perform pattern matching for known beneficial fusions, such as Conv-BN-ReLU, and may use Just-In-Time (JIT) or Ahead-of-Time (AOT) strategies to generate the final fused kernels.

FUSION PLANNER

Key Components of a Fusion Planner

A fusion planner is a compiler component that constructs an optimal plan for which operator groups to fuse by exploring a search space using a cost model. Its core subsystems work together to automate this critical optimization.

01

Computational Graph Representation

The fusion planner operates on an intermediate representation (IR) of the neural network, typically a dataflow graph where nodes are operators (e.g., Conv, MatMul, Add) and edges are data tensors. This representation must explicitly capture data dependencies and tensor shapes. The planner analyzes this graph to identify fusion groups—subgraphs of connected operators that are candidates for combination. Frameworks like MLIR or XLA HLO provide the structured IR necessary for this analysis.

02

Fusion Rule Engine & Pattern Matcher

This component applies a set of fusion heuristics to identify profitable fusion opportunities. It uses pattern matching to recognize common, beneficial subgraphs. For example:

  • Elementwise Fusion: Combining pointwise ops like Add, ReLU, Sigmoid.
  • Vertical Fusion: Merging a producer (e.g., Conv) with its direct consumer (e.g., BatchNorm).
  • Horizontal Fusion: Combining independent ops that share an input. Canonical patterns like Conv-BN-ReLU are hard-coded rules. More advanced planners use a pattern library that can be extended for new operator types.
03

Cost Model

The cost model is a predictive function that estimates the execution time, memory usage, or hardware utilization of a potential fused kernel versus the unfused baseline. It evaluates fusion profitability. Key inputs include:

  • Operator characteristics: FLOPs, memory bandwidth requirements.
  • Data access patterns: Stride, contiguity, reuse distance.
  • Hardware parameters: Cache sizes, register file limits, compute unit throughput. The model must balance memory-bound fusion (reducing DRAM traffic) against compute-bound fusion (increasing arithmetic intensity). An inaccurate cost model can lead to performance-degrading fusions.
04

Search & Optimization Algorithm

Given the exponential number of possible fusion groupings, the planner employs a search algorithm to find a near-optimal plan. Common strategies include:

  • Greedy Algorithms: Iteratively fuse the most profitable pair until no beneficial fusions remain.
  • Dynamic Programming: For sequences like chains of elementwise ops, using optimal substructure.
  • Graph Partitioning: Treating fusion as a problem of partitioning the computational graph into clusters, constrained by fusion legality (e.g., no cycles introduced). The output is a fusion plan—a mapping of each original operator to a specific fused kernel.
05

Kernel Code Generator Interface

Once a fusion plan is decided, the planner passes the specification of each fusion group to a kernel code generator. This backend component is responsible for producing the low-level, hardware-specific code (e.g., CUDA, Metal, Vulkan) for the fused kernel. The planner must provide a precise description of the fused operation's logic, including:

  • Fused computation schedule.
  • Memory access patterns.
  • Expected tensor shapes and data types. This handoff is crucial in compilers like TVM or Torch Inductor, where the planner and code generator are separate subsystems.
06

Hardware-Aware Profiling Data

Modern fusion planners are not purely static; they incorporate profile-guided optimization. They may:

  • Execute micro-benchmarks on the target hardware to calibrate the cost model.
  • Use just-in-time (JIT) fusion to make final decisions at runtime based on actual input shapes and device properties.
  • Cache profiling results for common operator patterns to accelerate future planning. This feedback loop allows the planner to adapt to different GPUs, CPUs, or specialized accelerators (NPUs), ensuring the fusion plan is tailored to the specific execution environment's characteristics.
OPTIMIZATION APPROACHES

Fusion Planner Strategies and Trade-offs

A comparison of core strategies employed by fusion planners, detailing their mechanisms, primary objectives, and inherent trade-offs.

StrategyMechanismPrimary GoalKey Trade-offTypical Use Case

Greedy Pattern Matching

Applies predefined fusion patterns (e.g., Conv-BN-ReLU) iteratively.

Fast compilation, predictable fusion.

Misses complex, non-canonical fusion opportunities.

Ahead-of-Time (AOT) compilation for known model architectures.

Cost-Model-Guided Search

Explores a space of possible fusions, evaluating each with a performance cost model.

Near-optimal fusion plan for a specific hardware target.

High compilation time due to search space exploration.

Just-in-Time (JIT) compilation for latency-critical inference.

Memory-Bound Optimization

Fuses operators to minimize intermediate tensor writes to DRAM.

Reduce off-chip memory bandwidth pressure.

May increase register pressure or limit parallelism within the fused kernel.

Models with many small, elementwise ops (e.g., activations, adds).

Compute-Bound Optimization

Fuses light operations (e.g., bias add) with heavy compute kernels (e.g., matmul).

Increase arithmetic intensity and hide latency of light ops.

Can be limited by available hardware registers and shared memory.

Dense linear algebra workloads and large matrix multiplications.

Vertical (Producer-Consumer) Fusion

Merges sequentially dependent operators along the dataflow graph.

Eliminate intermediate memory allocation and data movement.

Creates larger, more complex kernels that may exceed resource limits.

Chains of pointwise operations following a heavy compute node.

Horizontal (Parallel) Fusion

Merges independent operators that consume the same input tensor.

Amortize kernel launch overhead and improve data locality.

Requires compatible operator shapes and iteration spaces.

Multi-branch layers (e.g., inception modules, parallel attention heads).

Just-In-Time (JIT) Fusion

Performs fusion decisions dynamically at runtime based on concrete input shapes.

Maximize adaptability to dynamic input sizes and graph variations.

Runtime compilation overhead added to first inference call (cold start).

Models with dynamic control flow or variable-length sequences.

Ahead-of-Time (AOT) Fusion

Performs all fusion and kernel generation statically during an offline compile pass.

Zero runtime compilation overhead; predictable performance.

Inflexible to runtime shape changes; requires recompilation for new shapes.

Deployment to edge devices or production servers with fixed model specs.

COMPILER INFRASTRUCTURE

Fusion Planner Implementations

A fusion planner is a critical compiler component that constructs an optimal plan for grouping operators into fused kernels. Its implementation varies across modern deep learning compilers, each with distinct strategies for graph analysis, cost modeling, and code generation.

06

Cost Models & Search Algorithms

The core intelligence of any fusion planner is its cost model and search algorithm.

  • Analytical Cost Models: Estimate execution time based on hardware parameters (memory bandwidth, compute throughput) and operation characteristics (FLOP count, bytes accessed). They quickly evaluate the profitability of a candidate fusion.
  • ML-Based Cost Models: Used in systems like TVM, these are neural networks trained on profiling data to predict kernel runtime more accurately, especially for complex, fused kernels.
  • Search Algorithms:
    • Greedy Algorithms: Traverse the graph, fusing nodes if a local cost model predicts improvement. Fast but can be suboptimal.
    • Dynamic Programming: Explores all possible fusion partitions of a sequence (e.g., a chain of ops) to find a globally optimal plan.
    • Evolutionary/ML-Guided Search: Explores a broader space of possibilities, as used in auto-schedulers.
FUSION PLANNER

Frequently Asked Questions

A fusion planner is a critical compiler component in machine learning frameworks that automates the decision of which computational operators to combine for optimal performance. These questions address its core mechanisms and practical impact.

A fusion planner is a compiler component that constructs an optimal or near-optimal plan for which groups of operators to fuse into single kernels. It works by exploring a search space of possible fusions guided by a cost model that estimates the performance impact—weighing benefits like reduced kernel launch overhead and improved data locality against potential downsides like increased register pressure. The planner typically operates on a computational graph representation of a model, using algorithms to identify candidate fusion groups and decide on a final fusion strategy, which is then passed to a fusion compiler for kernel generation.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.