Confidential Computing Enclave

A secure area of a main processor that guarantees code and data loaded inside is protected with respect to confidentiality and integrity. A Confidential Computing Enclave is a specific instance of a TEE.

• Hardware Isolation: Protects data in use from the host OS, hypervisor, and other privileged software.
• Attestation: A cryptographic process that verifies the enclave's identity and integrity to a remote party before secrets are released.
• Key Technologies: Intel SGX, AMD SEV-SNP, and NVIDIA Confidential Computing.

The mechanism by which a relying party cryptographically verifies that a specific Confidential Computing Enclave is running genuine, unmodified code on authentic hardware. This is the trust anchor for multi-party genomic collaborations.

• Measurement: The enclave generates a cryptographic hash of its initial state.
• Verification: An attestation service validates the hash against a known-good build and confirms the hardware's provenance.
• Secrets Release: Only after successful attestation are decryption keys for sensitive genomic data provisioned to the enclave.

A hardware component integrated into the memory controller that transparently encrypts and decrypts data as it moves between the processor and main memory. This is the physical mechanism that secures the enclave's memory boundary.

• Transparent Operation: The encryption is invisible to the application running inside the enclave.
• Integrity Protection: Modern engines also prevent replay attacks and memory corruption by using authenticated encryption with counter-based trees.
• Performance: While it adds latency, the overhead is minimized by on-die caching and dedicated encryption pipelines.

A cryptographic paradigm that allows multiple parties to jointly compute a function over their private inputs without revealing those inputs to each other. It is a software-based alternative to Confidential Computing Enclaves.

• Comparison to Enclaves: SMPC relies on pure mathematics (e.g., secret sharing) rather than hardware trust, but is often orders of magnitude slower for complex genomic algorithms.
• Hybrid Models: Emerging architectures combine SMPC for lightweight control logic with hardware enclaves for heavy-duty model inference, balancing security and performance.

A dedicated, encrypted region of physical RAM reserved exclusively for Confidential Computing Enclave data and code. The EPC size is a critical resource constraint for genomic workloads.

• Capacity Limits: Early Intel SGX implementations limited the EPC to 128-256 MB, creating a bottleneck for large genomic models. Modern server-class processors now support multiple gigabytes.
• Paging Overhead: When the EPC is full, encrypted pages must be evicted to unprotected memory, incurring significant cryptographic and I/O overhead that can cripple performance for memory-intensive DNA sequence models.

A full virtual machine instance where the entire guest OS and all workloads are protected by hardware-based memory encryption, typically using technologies like AMD SEV-SNP or Intel TDX. This contrasts with the application-specific enclave model.

• Lift-and-Shift: CVMs allow existing genomic pipelines to run confidentially without code modification, unlike SDK-dependent enclave models.
• Trust Boundary: The trust boundary is the guest VM itself, not a specific function, simplifying deployment but expanding the Trusted Computing Base (TCB) that must be audited.