Inferensys

Glossary

FlashAttention

An exact-attention algorithm that minimizes high-bandwidth memory reads and writes between GPU HBM and SRAM by using tiling and recomputation, dramatically speeding up attention computation and reducing memory footprint for long sequences.
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IO-AWARE EXACT ATTENTION

What is FlashAttention?

An exact-attention algorithm that minimizes high-bandwidth memory reads and writes between GPU HBM and SRAM by using tiling and recomputation, dramatically speeding up attention computation and reducing memory footprint for long sequences.

FlashAttention is an IO-aware exact-attention algorithm that computes the standard self-attention operation without approximation. It achieves significant speedups by minimizing reads and writes between the slow, high-capacity GPU High Bandwidth Memory (HBM) and the fast, on-chip SRAM. The core innovation is fusing the attention operation into a single CUDA kernel through tiling, processing the attention matrix in blocks that fit entirely within SRAM.

To avoid materializing the full N x N attention matrix in HBM, FlashAttention employs recomputation of the softmax normalization statistics during the backward pass. This trades increased FLOPs for a dramatic reduction in memory I/O, lowering the memory complexity from O(N²) to O(N). The result is a 2-4x wall-clock speedup over standard PyTorch attention and the ability to train models on sequence lengths previously impossible due to memory constraints.

IO-Aware Exact Attention

Key Features of FlashAttention

FlashAttention is an algorithm that computes exact self-attention by optimizing data movement between GPU memory hierarchies, delivering significant speedups and memory savings for long sequences.

01

IO-Awareness: The Core Innovation

Standard attention implementations are memory-bound, spending most of their time reading and writing large intermediate matrices to GPU High Bandwidth Memory (HBM). FlashAttention is IO-aware, meaning it explicitly accounts for the speed hierarchy between slow HBM and fast on-chip SRAM. By minimizing HBM reads and writes, it shifts the bottleneck from memory bandwidth to compute utilization, achieving wall-clock speedups of 2-4x over optimized baselines like PyTorch's scaled_dot_product_attention.

02

Tiling: Block-by-Block Computation

To avoid materializing the full N x N attention matrix in HBM, FlashAttention uses tiling. The algorithm splits the input sequences (Q, K, V) into blocks that fit entirely within SRAM. Attention is computed incrementally block-by-block, with intermediate softmax statistics carefully tracked and rescaled. This allows exact attention computation without ever storing the full quadratic intermediate matrix, reducing peak memory from O(N²) to O(N).

03

Recomputation: Trading Compute for Memory

In the backward pass, standard attention saves the large attention matrix from the forward pass for gradient calculation. FlashAttention discards this matrix and instead recomputes it on-the-fly during the backward pass using the stored softmax normalization statistics. This trades a modest increase in FLOPs for a dramatic reduction in memory footprint, enabling training with 4-8x longer sequences on the same hardware without running out of memory.

04

Exact Attention, Not an Approximation

Unlike sparse or low-rank attention approximations (e.g., Longformer, Linformer), FlashAttention computes mathematically exact self-attention. The output is numerically identical to standard attention up to floating-point rounding errors. This means there is no accuracy trade-off—models trained with FlashAttention achieve identical perplexity and downstream task performance while benefiting from the speed and memory advantages.

05

FlashAttention-2: Parallelism & Work Partitioning

The second iteration, FlashAttention-2, significantly improves GPU utilization by redesigning the work partitioning strategy. It reduces non-matmul FLOPs, parallelizes over the sequence length dimension (previously parallelized only over batch and heads), and distributes work more evenly across thread blocks. This achieves 2x speedup over the original FlashAttention and pushes GPU utilization to near theoretical limits, reaching up to 73% of peak FLOPs on A100 GPUs.

06

FlashAttention-3: Hopper Architecture Optimization

FlashAttention-3 targets NVIDIA's Hopper GPU architecture (H100), exploiting new hardware features like WGMMA instructions for asynchronous Tensor Core operations and TMA (Tensor Memory Accelerator) for hardware-accelerated data movement. It introduces interleaved block-wise matmul and softmax scheduling to hide memory latency. On H100 GPUs, FlashAttention-3 achieves 1.5-2.0x speedup over FlashAttention-2 and reaches up to 740 TFLOPS, representing 75% of theoretical peak performance.

FlashAttention

Frequently Asked Questions

Clear, technically precise answers to the most common questions about the FlashAttention algorithm, its mechanisms, and its impact on large language model training and inference.

FlashAttention is an exact-attention algorithm that computes the standard Transformer self-attention output identically to the conventional implementation but with dramatically reduced memory reads and writes between GPU high-bandwidth memory (HBM) and on-chip SRAM. It works by employing two key techniques: tiling, which decomposes the large attention matrix into smaller blocks that fit entirely within SRAM, and recomputation, which re-derives the softmax normalization statistics during the backward pass instead of storing the full intermediate attention matrix. By fusing the entire attention operation into a single CUDA kernel, FlashAttention avoids materializing the quadratic N x N attention matrix in HBM, reducing peak memory from O(N²) to O(N) and delivering 2-4x wall-clock speedups on long sequences. The algorithm is mathematically exact—it produces the same output and gradients as standard attention up to numerical precision—making it a drop-in replacement for existing attention implementations without any model retraining or architecture modification.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.