Energy Budget

This is the baseline energy draw required to keep the device's core systems active, even when idle. It is determined by the MCU's sleep/leakage current and the power management of essential peripherals. For a device expected to last years on a coin-cell battery, minimizing static consumption is paramount. For example, an MCU in a deep sleep mode might draw < 10 µA, while active sensing and wireless radios can increase this by orders of magnitude.

The energy expended to perform the actual mathematical operations of model inference or training. This cost scales with:

• Model Complexity: The number of multiply-accumulate (MAC) operations.
• Compute Precision: Low-precision (e.g., INT8) arithmetic consumes significantly less energy than FP32.
• Processor Efficiency: Energy per operation (e.g., pJ/MAC) varies drastically between a general-purpose Cortex-M core and a dedicated Neural Processing Unit (NPU). A single inference on a simple model might cost ~10-100 µJ, while a local training step could consume millijoules.

Fetching model weights and moving activation data between memory hierarchies (Flash, SRAM, registers) is often more energy-intensive than the computation itself. Key factors include:

• Memory Technology: SRAM access is faster but more power-hungry than Flash reads.
• Data Movement: Minimizing transfers between off-chip and on-chip memory is critical.
• Model Sparsity: Leveraging sparse models and sparse updates reduces the number of memory accesses required. Techniques like weight pruning directly target this component of the energy budget.

In federated learning, transmitting model updates is a major energy drain, often dominating the budget. The cost is a function of:

• Update Size: Compressed, quantized, or sparse updates reduce payload size.
• Transmission Power: The radio's output power level, which scales with distance and environmental factors.
• Protocol Efficiency: Connection setup, handshakes, and retransmissions add overhead. Sending a 100 KB model update via Bluetooth Low Energy may consume ~10-50 mJ, far exceeding a local compute step.

The energy required to sample data for on-device learning. This includes:

• Sensor Power-Up Time: Many sensors have a significant warm-up period before stable readings.
• Sampling Rate & Resolution: Higher fidelity data collection increases energy use.
• On-Device Preprocessing: Running FFTs or filters on raw sensor streams adds compute cost. Optimizing the duty cycle—how often and for how long sensors are active—is a primary lever for managing this budget component.

Energy consumption directly translates to heat generation and voltage drop, which impose hard limits.

• Thermal Throttling: Sustained high compute can trigger clock speed reduction, degrading performance and altering the energy-per-operation ratio.
• Brown-Out Risk: High-current draws can cause a temporary voltage drop, risking MCU resets.
• Battery Chemistry Effects: Non-linear discharge curves and increased internal resistance at low states of charge affect available power. These constraints make peak power draw as important as total energy in the budget.

The core optimization problem in federated edge learning. Increasing local computation (more training epochs) can produce a more refined model update, potentially reducing the total number of communication rounds required for convergence. However, each local epoch consumes energy. The optimal point minimizes total system energy, balancing the energy cost of compute (Joules per FLOP) against the often dominant energy cost of wireless transmission (Joules per bit). For TinyML, strategies like Local SGD with adaptive rounds are used to find this equilibrium.

Techniques to drastically reduce the communication energy burden, which is often the largest consumer of a device's energy budget.

• Sparse Updates: Only transmit a small fraction of the most significant gradient or weight changes (e.g., top-k by magnitude). This reduces the payload size from megabytes to kilobytes.
• Quantized Updates: Compress model updates using low-bitwidth quantization (e.g., 1-bit SignSGD, 8-bit integers) before transmission. This reduces the number of bits sent per parameter. Combined, these methods can reduce communication energy by over 99% compared to sending full-precision, dense updates.

Automated design of ultra-efficient neural network architectures tailored to a device's specific hardware and energy profile. Instead of manually designing models, Hardware-Aware NAS uses search algorithms to find Pareto-optimal architectures that maximize accuracy while minimizing a joint cost function of model size, FLOPs, and measured energy consumption on the target MCU or NPU. This results in models whose operational patterns (activation sparsity, memory access) are inherently aligned with the hardware's most energy-efficient execution paths.

A hardware-level technique where the operating voltage and clock frequency of the processor are dynamically adjusted based on computational load. For federated learning clients:

• Training Phase: CPU/NPU frequency is scaled up to complete local epochs quickly, then powered down.
• Idle/Communication Phase: Frequency is scaled to minimum to conserve energy. Advanced schedulers predict compute needs for a training round and apply race-to-idle or energy-proportional computing strategies to minimize the energy-time integral for the task.

Intelligent selection of which devices participate in a federated round based on their available energy state, not just data or capability. The server prioritizes clients with:

• High battery state-of-charge or connected to a power source.
• Favorable channel conditions (high signal strength), which reduces transmission energy.
• Sufficient idle thermal headroom to avoid thermal throttling. This extends the federation's lifetime by avoiding energy-critical devices and reduces dropouts, improving overall system efficiency. It often uses lightweight energy profiling reports from clients.

Low-level software optimizations that directly reduce the active energy consumption of on-device training loops.

• Optimized Kernels: Use of hand-tuned, assembly-level linear algebra routines for the target MCU (e.g., CMSIS-NN) that maximize operations per Joule.
• Aggressive Sleep Scheduling: The embedded FL runtime maximizes time in deep sleep mode. It batches sensor data collection, wakes to perform a burst of compute (training), transmits the update, and immediately returns to sleep. The goal is to minimize the duty cycle where power-hungry components (CPU, radio) are active.

A compute constraint is the limitation imposed by the available processing power of a resource-constrained device, measured in operations per second (OPS) or clock speed. This directly limits the complexity of machine learning models and training algorithms that can be executed within a given energy budget.

• Defines Model Feasibility: Determines if a neural network layer or optimizer step can complete before a device's battery is depleted or its thermal limits are reached.
• Interacts with Energy Budget: Higher compute utilization typically correlates with higher instantaneous power draw, forcing trade-offs between task duration and peak power consumption.
• Examples: A 50 MHz ARM Cortex-M4 microcontroller has a fundamentally different compute constraint than a 1.5 GHz application processor, dictating different federated learning strategies.

Memory footprint is the total amount of volatile (RAM) and non-volatile (Flash) memory consumed by a machine learning model's parameters, activations, gradients, and runtime buffers. Managing this footprint is essential for staying within an energy budget, as memory access is a significant contributor to power consumption.

• Energy Cost of Access: Reading from and writing to Flash memory consumes more energy than RAM access, which in turn consumes more than compute operations on many MCUs. A large model forces frequent, high-energy memory transactions.
• On-Device Training Impact: Training requires storing the model, an optimizer state (e.g., momentum), gradients, and a batch of data, often doubling or tripling the memory footprint versus inference-only deployment.
• Optimization Target: Techniques like model sparsification, quantization, and selective updating are used primarily to reduce the memory footprint, which subsequently reduces the energy cost per federated learning round.

Battery drain is the rate at which a device's stored electrical energy is depleted, measured in milliwatts (mW) or as a percentage of capacity per hour. It is the real-time consequence of exceeding an energy budget.

• Primary Metric for Lifetime: The integral of power draw over time equals total energy consumed. High drain shortens operational lifespan between charges or battery replacements.
• Component Breakdown: In federated edge learning, drain is dominated by:
  • Radio Communication: Transmitting model updates is often the most expensive operation.
  • On-Device Training: The sustained compute load of backpropagation.
  • Sensor Activation: Collecting the local data used for training.
• Design Imperative: Federated learning protocols for TinyML must minimize the frequency and size of updates (communication drain) and leverage ultra-efficient training loops (compute drain) to manage overall battery drain.

An availability window is the limited period during which a federated learning client is powered on, connected to a network, idle, and has sufficient resources to participate in a training round. The energy budget directly determines the size and frequency of these windows.

• Energy-Limited Availability: A device with a tight daily energy budget may only be able to "wake up" for a 5-minute training window once per day when powered by a small solar cell.
• Scheduling Constraint: The federated learning orchestrator must schedule training rounds to coincide with client availability windows, which are dictated by energy harvesting cycles, user interaction patterns, or thermal limits.
• Partial Participation: Because not all devices can be available simultaneously (due to energy constraints), partial participation is a fundamental assumption in federated edge learning system design.

Thermal throttling is a hardware protection mechanism where a processor automatically reduces its clock speed to lower power consumption and heat generation when a critical temperature threshold is exceeded. It is a hard physical limit that can invalidate an energy budget if not accounted for.

• Consequence of Sustained Compute: Intensive on-device training can quickly raise die temperature, especially in small, sealed embedded devices with passive cooling.
• Impacts Performance and Energy: Throttling increases the time required to complete a fixed amount of compute, which can paradoxically increase total energy consumption for the task and disrupt federated learning round deadlines.
• Mitigation Strategy: Federated learning algorithms for TinyML must include lightweight, low-intensity training steps that stay within the device's sustainable thermal envelope, a key aspect of practical energy budget planning.

A sparse update in federated learning is a client model update (e.g., gradient or weight delta) where only a small subset of the parameters have non-zero values. This is a critical technique for adhering to communication and energy budgets on edge devices.

• Reduces Communication Cost: Transmitting only non-zero values and their indices drastically reduces the payload size, minimizing the energy-intensive radio transmission phase of federated learning.
• Reduces Compute Cost: Computing gradients only for a sparse mask reduces the number of operations during local training, lowering the compute-related energy consumption.
• Induced via Pruning: Model sparsification techniques create a static or dynamic sparse mask, ensuring that the majority of updates are zero, making the update inherently efficient and energy-budget-friendly.