Battery Drain

The total amount of electrical energy allocated for a computational task, such as a federated learning round or an inference cycle. For battery-powered devices, this is a finite resource derived from battery capacity and desired operational lifetime. System design involves partitioning this budget across:

• Sensor sampling and data acquisition.
• On-device preprocessing (e.g., FFT, filtering).
• Local model training (forward/backward passes).
• Secure communication of model updates.
• Idle/sleep state power draw. Exceeding the budget leads to premature device failure or necessitates unsustainable recharge cycles.

The limitation imposed by the available processing power of a microcontroller, measured in operations per second (OPS) or clock speed (MHz). This restricts the complexity of models and training algorithms. Key impacts on battery drain:

• Complex models require more cycles, keeping the CPU active longer and consuming more energy.
• Inefficient algorithms with high iteration counts drain batteries through prolonged computation.
• Hardware accelerators like Neural Processing Units (NPUs) can execute specific operations (e.g., matrix multiplies) with far greater energy efficiency than a general-purpose CPU, directly reducing drain for intensive workloads.

Performing neural network computations using numerical formats with fewer bits than standard 32-bit floating-point (e.g., 8-bit integers, 16-bit floats). This is a primary technique for reducing battery drain:

• Reduced memory bandwidth lowers energy per operation.
• Smaller circuits in hardware accelerators consume less power.
• Enables integer-only inference, eliminating power-hungry floating-point units.
• Quantization-Aware Training (QAT) and Post-Training Quantization (PTQ) are essential methodologies to prepare models for efficient low-precision execution on edge devices.

A suite of techniques designed to minimize the energy cost of wireless communication, which is often the most battery-intensive phase of federated learning. Core methods include:

• Sparse Updates: Transmitting only the most significant changed parameters (gradients/weights).
• Model Compression: Applying lossy compression (e.g., quantization, pruning) to updates before transmission.
• Reduced Communication Rounds: Designing algorithms that converge in fewer rounds.
• Local Computation vs. Communication Trade-off: Increasing local computation (e.g., more local epochs) can sometimes reduce total energy by enabling sparser, less frequent communication.

The lightweight software library on a microcontroller that manages the federated learning client protocol. Its efficiency directly dictates battery drain. An optimized runtime implements:

• Energy-Aware Scheduling: Executing training during natural device activity or high energy availability (e.g., when charging).
• Sleep Mode Management: Aggressively putting the MCU and radio into low-power states between compute tasks.
• Memory Management: Minimizing dynamic allocation to reduce power-hungry RAM access.
• Hardware Abstraction: Leveraging low-level power control registers and accelerator APIs for maximal efficiency.

A hardware protection mechanism where a processor automatically reduces its clock speed to lower power consumption and heat generation when a critical temperature is exceeded. For battery-powered TinyML devices:

• Intensive on-device training can quickly generate excess heat.
• Throttling slows computation, increasing the time (and thus total energy) required to complete a training round.
• In extreme cases, it can cause premature termination of a learning task.
• System design must account for thermal dissipation and may need to limit compute intensity to avoid triggering throttling, creating a direct link between thermal design and battery lifespan.