Fault Injection Attack

A technique that momentarily drops or spikes the supply voltage to a processor, causing setup time violations in critical paths. By precisely timing a voltage sag during a security check—such as a signature verification—the attacker forces the chip to skip the instruction or accept an invalid result.

• Target: Secure boot ROMs and authentication gates
• Equipment: Crowbar circuit or programmable power supply
• Effect: Bypasses firmware integrity checks, allowing malicious model weights to load
• Countermeasure: On-chip voltage monitors and glitch detectors

Injects a deliberately shortened clock cycle to violate the critical path timing of a specific instruction. By forcing a premature clock edge, the attacker causes the target flip-flop to sample an unstable value, corrupting the result of a comparison or branch decision.

• Target: Instruction decode and execution stages
• Equipment: FPGA-based clock manipulator or pulse generator
• Effect: Transforms a conditional jump into a no-op, bypassing authentication
• Countermeasure: Redundant sampling and temporal redundancy

Uses a high-voltage pulse through a probe coil to induce eddy currents on the chip surface, locally disrupting transistor switching. EMFI is non-invasive and spatially precise, allowing attackers to target a single flip-flop or logic gate without decapping the chip.

• Target: Cryptographic accelerators and key storage
• Equipment: EMFI probe tip, high-voltage pulse generator, XY positioning stage
• Effect: Flips bits in a hardware security module during AES key extraction
• Countermeasure: Active shielding and EM sensors on die

Employs a focused infrared or visible laser pulse to ionize a specific transistor in the chip's active layer. By illuminating a single gate, the attacker creates a transient photocurrent that flips the logic state. LFI offers the highest spatial precision and requires backside decapping of the chip package.

• Target: Individual SRAM cells storing security flags
• Equipment: Near-infrared laser, microscope objective, precision stage
• Effect: Single-bit flips in register files or memory-mapped security fuses
• Countermeasure: Light sensors and spatially redundant logic

Exploits the temperature-dependent behavior of semiconductor physics by heating or cooling the chip beyond its rated operating range. Extreme temperatures alter carrier mobility and threshold voltages, causing timing violations or forcing DRAM cells to retain data longer than intended—enabling cold-boot style attacks.

• Target: DRAM retention and random number generators
• Equipment: Peltier cooler, heat gun, or liquid nitrogen
• Effect: Extends data remanence in memory, exposing model weights after power-down
• Countermeasure: Temperature sensors triggering immediate memory wipe

Manipulates the substrate or well bias voltage of transistors to shift their threshold voltage (Vth). By altering the body bias, the attacker can slow down or speed up specific logic paths, selectively violating setup or hold times in targeted circuits without affecting the entire chip.

• Target: Secure enclaves and trusted execution environments
• Equipment: Precision voltage source connected to substrate pins
• Effect: Induces timing faults in cryptographic comparisons while leaving other logic intact
• Countermeasure: On-chip body bias monitors and adaptive clocking

A non-invasive attack that extracts secrets by observing physical information leakage from a system rather than exploiting software bugs. Attackers monitor timing variations, power consumption, electromagnetic emissions, or acoustic signatures during cryptographic operations or model inference. A Simple Power Analysis (SPA) directly interprets power traces, while Differential Power Analysis (DPA) uses statistical methods to correlate power consumption with data values. These attacks can recover model weights, encryption keys, and architectural details without leaving physical evidence of tampering.

A specific fault injection technique that momentarily drops or spikes the supply voltage to a processor, causing transistors to skip instructions or misinterpret opcodes. By precisely timing a voltage dip during a critical security check—such as a branch instruction comparing an authentication flag—an attacker can force the processor to take the authenticated path regardless of the actual credential. Common targets include:

• Boot ROM verification bypasses
• Secure boot signature checks
• JTAG lock bit manipulation Defenses include brown-out detectors, voltage monitors, and hardware redundancy with dual-rail logic.

A non-contact attack that uses a high-voltage pulse through a probe coil to induce localized eddy currents on a chip's surface. This creates transient faults in specific flip-flops or logic gates without requiring physical modification. EMFI offers spatial precision—attackers can target individual cryptographic units or memory controllers while leaving other components unaffected. The technique is particularly dangerous because it can be performed through chip packaging and heat spreaders, making it viable against production-deployed AI accelerators without visible tampering.

A highly precise attack that uses focused infrared or visible laser pulses to induce photoelectric effects in specific transistors. By decapsulating a chip and targeting individual gates, attackers can:

• Set or reset specific flip-flops
• Induce timing violations in critical paths
• Bypass redundancy checks in lockstep cores Modern techniques use two-photon absorption to inject faults through the silicon substrate from the backside, defeating front-side metal shielding. This represents the highest precision fault injection method, capable of defeating many hardware countermeasures.

A fault injection method that manipulates the external clock signal feeding a processor to violate setup and hold times. By injecting a narrower-than-specified clock pulse, the attacker causes some flip-flops to capture incorrect values while others operate normally. This creates timing violations that can skip instructions or corrupt data in predictable ways. Clock glitching is often combined with overclocking to stress specific circuit paths. Defenses include internal clock monitoring, glitch detectors, and synchronized dual-core execution that compares outputs.