Hard Real-Time

Deterministic execution is the foundational property where the timing and order of all system operations are predictable and repeatable for identical inputs and conditions. This is not about raw speed, but about bounded latency and the absence of non-deterministic behaviors like garbage collection pauses or unpredictable cache misses. In robotic control, a deterministic 1ms control loop is vastly more valuable than a faster but variable 0.1-10ms loop.

• Requires analysis of Worst-Case Execution Time (WCET) for all tasks.
• Contrasts with general-purpose computing, where average performance is prioritized.

In a hard real-time system, timeliness is a dimension of correctness. A computationally perfect result delivered after its deadline is functionally incorrect and constitutes a system failure. This shifts the design paradigm from optimizing for throughput to guaranteeing latency bounds.

• Example: A motor controller must compute and apply a corrective torque within the physical system's time constant. A late computation can lead to instability or a collision.
• Schedulability analysis is used to mathematically prove all tasks will meet deadlines under worst-case conditions.

The system must guarantee a maximum, bounded response time to critical external events, such as a sensor reading or fault signal. This is managed through Interrupt Service Routines (ISRs) and prioritized scheduling.

• Interrupt Latency (time from signal to ISR start) and Interrupt Service Time must be characterized and minimized.
• Priority-based preemption ensures a high-priority interrupt immediately suspends a lower-priority task.
• Jitter, or variation in response time, must be tightly controlled, as it introduces noise into control loops.

Hard real-time systems rely on mathematical proofs, not testing alone, to verify timing constraints. Schedulability analysis uses models of task periods, execution times, and priorities to demonstrate all deadlines will be met.

• Common Algorithms: Rate-Monotonic Scheduling (RMS) for static priorities; Earliest Deadline First (EDF) for dynamic priorities.
• Utilization Bound: For RMS, a theoretical CPU utilization limit (e.g., ~69% for many tasks) provides a simple pass/fail test.
• Requires accurate WCET analysis for all critical code paths.

To ensure predictability, system resources (CPU, memory, network, I/O) must be explicitly managed and isolated. Uncontrolled resource contention is a primary source of deadline misses.

• Memory Management: Often uses static allocation or pool allocators to avoid non-deterministic heap fragmentation.
• CPU Arbitration: Uses priority-aware schedulers and techniques to mitigate priority inversion (e.g., priority inheritance).
• I/O and Buses: Use of Time-Sensitive Networking (TSN) or DMA controllers to ensure data transfer deadlines.

Given the catastrophic cost of failure, hard real-time systems incorporate dedicated mechanisms to detect and handle faults within their timing constraints.

• Watchdog Timers: Hardware timers that reset the system if not regularly serviced, catching software hangs.
• Redundancy: Dual or triple modular redundancy for critical computation paths.
• Error Detection and Correction (EDAC): For memory in radiation-prone environments.
• These mechanisms themselves must operate with hard real-time guarantees.

In modern drive-by-wire systems, an electronic control unit (ECU) must process a brake pedal sensor input and command hydraulic actuators within a strict deadline (typically < 10ms). Missing this deadline means the vehicle fails to decelerate as commanded, leading to a collision. This is a safety-critical hard real-time function governed by standards like ISO 26262 (ASIL D).

Aircraft flight control computers (FCCs) must process pilot inputs and sensor data (e.g., air data, inertial measurement) to command control surface actuators (ailerons, elevators) within millisecond-level deadlines. A missed computation cycle can cause instability or loss of control. These systems use redundant, lockstep processors and are certified to DO-178C Design Assurance Level A.

• Actuator Control Loop: Periods range from 1-20ms.
• Triple Modular Redundancy (TMR): Common architecture for fault tolerance.

A collaborative robot (cobot) uses proximity sensors (e.g., LiDAR, safety-rated laser scanners) to detect a human intrusion into a shared workspace. The safety-rated controller must halt robot motion within the safe separation distance calculation, a deadline often under 50ms. A deadline miss results in physical injury. This is implemented via Safety PLCs or dedicated safe motion monitoring hardware.

A critical care ventilator must deliver breaths at precise intervals and pressure/volume profiles dictated by patient needs. The control loop that reads airway pressure sensors and adjusts the proportional solenoid valve has a hard deadline tied to the respiratory cycle (e.g., every 20ms for a breath rate of 30/min). Failure to compute the control output in time can cause barotrauma or insufficient ventilation. These systems are Class III medical devices with rigorous validation.

Digital protective relays monitor current and voltage waveforms on high-voltage transmission lines. Upon detecting a fault (e.g., a short circuit), they must issue a trip signal to a circuit breaker within 1-3 cycles of AC power (16.7-50ms). Missing this deadline allows fault current to persist, risking equipment destruction, fire, or cascading blackouts. These systems use dedicated DSPs and are tested for Worst-Case Execution Time (WCET).

• Function: Isolate faulted sections.
• Consequence of Miss: Catastrophic equipment damage, widespread outage.

An ABS controller continuously monitors wheel speed sensors. When it detects an impending wheel lock-up, it must compute and command pulse-width modulated (PWM) signals to hydraulic valves to modulate brake pressure. This control loop operates at a high frequency (50-100Hz), and missing a deadline reduces braking effectiveness, increasing stopping distance and potentially causing loss of vehicle control. It is a classic embedded hard real-time control loop.

A system property where the timing, order, and output of task execution are predictable and repeatable for identical inputs and initial conditions. This is non-negotiable for hard real-time systems, as it allows engineers to formally prove that all deadlines will be met under worst-case scenarios. It contrasts with the statistical performance guarantees of general-purpose computing.

• Key Enablers: Static memory allocation, cache locking, time-triggered architectures.
• Violations: Non-deterministic garbage collection, dynamic memory allocation, unpredicted branch prediction.

The maximum possible time a specific task or code segment can take to execute on given hardware, considering all possible inputs and system states. WCET analysis is a critical step in schedulability analysis for hard real-time systems.

• Analysis Methods: Static analysis (examining the code), measurement-based analysis (profiling), or hybrid approaches.
• Importance: If the sum of all tasks' WCETs exceeds the system's period, a deadline miss is guaranteed, constituting a system failure.

The variation in latency or the deviation from a periodic signal's true periodicity. In control loops, excessive jitter can destabilize systems by causing inconsistent sampling and actuation.

• Sources: Variable interrupt latency, shared resource contention, non-deterministic scheduling.
• Impact: A control loop with a 1ms period and ±0.3ms jitter effectively has an unpredictable period between 0.7ms and 1.3ms, degrading performance and potentially causing instability.

A static priority preemptive scheduling algorithm where tasks with shorter periods are assigned higher priorities. It provides a simple, sufficient (but not necessary) schedulability test: a set of n periodic tasks is guaranteed to be schedulable if total CPU utilization is less than n(2^(1/n) - 1).

• Assumptions: Independent tasks, deadlines equal to periods, zero context-switch overhead.
• Use Case: Foundational theory for designing predictable periodic task sets in embedded control.

A system design paradigm where all communication and task execution are driven by the progression of a global time base. Actions occur at predetermined instants, making the system highly deterministic and testable.

• Contrasts with event-triggered architectures, which react to external events.
• Benefits: Eliminates resource contention, simplifies validation, provides inherent fault detection via expected messages at specific times.
• Application: Common in aerospace (e.g., ARINC 653) and automotive (AUTOSAR) safety-critical systems.