Context Switch

The Program Counter is the CPU register that holds the memory address of the next instruction to execute. During a context switch, this value must be saved to the outgoing task's Process Control Block (PCB) and restored from the incoming task's PCB. This ensures execution resumes at the correct point. For example, if a motor control ISR is interrupted, the PC must be saved so the ISR can complete after the higher-priority task finishes.

The register file comprises all general-purpose (e.g., R0-R15 on ARM), floating-point, and specialized CPU registers (e.g., status registers). Their entire state constitutes the processor's "working memory." A context switch requires:

• Saving all live register values to the outgoing task's stack or PCB.
• Restoring the previously saved register set for the incoming task. This operation is memory-intensive; architectures with larger register sets (e.g., for vector/SIMD operations) incur higher overhead. Techniques like lazy saving only save registers actually used.

The Process Control Block is the kernel's in-memory data structure that stores all metadata needed to manage a task's execution. It is the primary data structure manipulated during a context switch. Key fields include:

• Task State: Running, ready, blocked.
• CPU State: Saved registers, program counter.
• Memory Management Info: Page table base pointers (e.g., CR3 on x86).
• Scheduling Info: Priority, time quantum, scheduling policy.
• I/O Status: Pointers to open files, allocated devices. The switch involves updating the current PCB pointer in the kernel to point to the incoming task's PCB.

For systems with virtual memory, the Memory Management Unit (MMU) context must be switched. This primarily involves loading the page table base register (e.g., TTBR0_EL1 on ARM, CR3 on x86) with the address of the incoming task's page tables. This operation often triggers a Translation Lookaside Buffer (TLB) flush or requires an Address Space Identifier (ASID) to avoid flushing, as reloading the TLB adds significant latency. In real-time embedded systems, tasks often share a single address space to eliminate this overhead entirely.

Each task typically has two stacks: a user stack and a private kernel stack. When a task enters the kernel (via a system call, interrupt, or exception), it switches to its dedicated kernel stack. During a context switch, the kernel must:

• Save the current stack pointer (SP) for the outgoing task's kernel stack.
• Load the SP with the pointer to the incoming task's kernel stack. This ensures the kernel has a clean, per-task stack for handling system calls and interrupts, preventing corruption. The kernel stack pointer is stored in the PCB.

The scheduler is the kernel component that selects the next task to run based on policy (e.g., Rate-Monotonic, EDF). The dispatcher is the low-level code that performs the actual context switch. The sequence is:

1. Trigger: Interrupt, system call, or task block/unblock.
2. Save State: Dispatcher saves PC, registers to outgoing PCB.
3. Scheduler Invocation: Kernel runs scheduler algorithm.
4. Context Restore: Dispatcher loads PC, registers from incoming PCB.
5. Resume Execution: CPU jumps to the restored PC. The time from trigger to resume is the total context switch latency, a critical metric for real-time systems.

Scheduling is the algorithmic process by which an RTOS decides which ready task to execute next on the CPU. The scheduler's policy directly impacts context switch frequency and system responsiveness. Key algorithms include:

• Rate-Monotonic Scheduling (RMS): A static, preemptive policy where tasks with shorter periods get higher priority.
• Earliest Deadline First (EDF): A dynamic policy that prioritizes the task with the closest deadline. The scheduler initiates a context switch when a higher-priority task becomes ready or when the currently running task blocks (e.g., waiting for an I/O event).

Worst-Case Execution Time (WCET) is the maximum possible time a specific task or code segment can take to execute on given hardware, considering all possible inputs and system states. It is a critical metric for real-time system design. To guarantee all deadlines are met, system designers perform schedulability analysis, which sums the WCET of all tasks and includes the overhead of context switches. An underestimated WCET or unaccounted-for switch overhead can lead to missed deadlines and system failure.

An Interrupt Service Routine (ISR) is a short, time-critical function that executes in immediate response to a hardware interrupt (e.g., from a sensor or timer). Handling an interrupt often triggers a context switch from the current task to the ISR. In real-time systems, ISRs are kept extremely brief to minimize latency for other interrupts and task execution. A common pattern is for the ISR to simply acknowledge the interrupt and release a semaphore, allowing a higher-priority task (Deferred Interrupt Handler) to process the data, which involves another context switch.

Priority inversion is a hazardous condition in preemptive, priority-scheduled systems where a high-priority task is forced to wait indefinitely for a lower-priority task to release a shared resource (like a mutex). This can occur during a sequence of context switches and directly violates the intended scheduling policy, causing deadline misses. Mitigation techniques include:

• Priority inheritance: The low-priority task holding the resource temporarily inherits the priority of the waiting high-priority task.
• Priority ceiling protocols. These protocols add complexity to the context switch logic but are essential for reliability.

Deterministic execution means a system's timing behavior is predictable and repeatable for identical inputs and conditions. This is a foundational requirement for hard real-time robotic control. Context switches are a primary source of non-determinism if their latency is variable. An RTOS achieves determinism by:

• Using fixed, known context switch times.
• Eliminating features with unpredictable timing (e.g., garbage collection, dynamic paging).
• Providing precise, bounded latencies for interrupts and scheduler invocations. Every microsecond of jitter in a context switch translates directly into jitter in a control loop's period.