Chiplet

Chiplet architecture decomposes a large, monolithic SoC into smaller functional blocks, or chiplets, each manufactured on the optimal semiconductor process node. This enables heterogeneous integration, where a CPU corelet built on a leading-edge 3nm node can be packaged alongside an I/O chiplet on a mature 28nm node and an analog/RF chiplet on a specialized 45nm node. The primary benefits are:

• Cost Reduction: Uses smaller, higher-yield dies and cheaper legacy nodes where possible.
• Performance Optimization: Matches each function to the best-performing or most power-efficient technology.
• Design Flexibility: Allows mixing and matching chiplets from different vendors to create custom solutions.

The performance of a chiplet-based system is defined by the density and bandwidth of the connections between dies. This relies on advanced packaging technologies that go beyond traditional printed circuit boards:

• 2.5D Packaging: Chiplets are placed side-by-side on a passive silicon interposer, which contains a dense mesh of wiring to connect them with very short, high-bandwidth links.
• 3D Packaging: Chiplets are stacked vertically using through-silicon vias (TSVs) and micro-bumps, creating ultra-short vertical connections for extreme bandwidth and reduced latency between logic and memory stacks.
• High-Bandwidth Interconnect Protocols: Standardized die-to-die (D2D) interfaces like Universal Chiplet Interconnect Express (UCIe) provide a common physical layer and protocol stack, enabling interoperability between chiplets from different foundries.

A core driver for chiplets is the economic challenge of manufacturing large, monolithic dies. Defect rates increase with die area, making large SoCs prohibitively expensive. By splitting a design into smaller chiplets:

• Defect Isolation: A flaw in one small chiplet does not scrap the entire large die, significantly improving overall yield.
• IP Reuse & Scalability: Proven, pre-validated chiplets (e.g., a specific CPU core cluster or memory controller) can be reused across multiple product generations and scaled (e.g., adding more core chiplets) without a full redesign.
• Reduced Time-to-Market: Designing and verifying smaller functional blocks is faster than a full monolithic SoC, and mixing known-good chiplets accelerates system assembly.

Chiplet architectures enable more granular and efficient power management, which is critical for edge AI devices operating within strict power envelopes.

• Voltage/Frequency Islands: Each chiplet can operate at its own optimal voltage and frequency, independent of others. A high-performance NPU chiplet can run fast while an I/O chiplet remains in a low-power state.
• Proximity to Memory: 3D stacking allows memory chiplets (like High-Bandwidth Memory) to be placed directly on top of a processor chiplet, drastically reducing the energy cost of data movement—a principle aligned with Compute-in-Memory (CIM) concepts.
• Thermal Density: While inter-die connections are efficient, stacking compute-dense chiplets creates localized hot spots. Advanced thermal modeling and heterogeneous integration (placing cooler chiplets near hot ones) are required for effective heat dissipation.

The shift to chiplets introduces new complexities at the system architecture and software levels:

• Coherent Interconnects: Maintaining memory coherence and cache consistency across multiple discrete chiplets requires sophisticated Network-on-Chip (NoC) extensions and coherency protocols.
• Testing & Validation: System-level testing must verify not only each chiplet but also all inter-die connections and the performance of the complete assembled system.
• Software & Tooling: Operating systems and compilers must be aware of the Non-Uniform Memory Access (NUMA)-like characteristics introduced by chiplets, where access latency and bandwidth vary depending on which chiplet holds the data.

The success of chiplet architecture depends on the development of a robust ecosystem and open standards to ensure interoperability.

• Universal Chiplet Interconnect Express (UCIe): An industry consortium standard defining the physical layer, protocol stack, and software model for die-to-die connectivity, aiming to create a 'plug-and-play' ecosystem.
• Advanced Interface Bus (AIB): Intel's open-source physical-layer specification for chiplet interconnection, contributed to the CHIPS Alliance.
• Design & Packaging Standards: New standards are emerging for chiplet form factors, testing methodologies, and security models to enable a multi-vendor marketplace of compatible chiplets.

Advanced packaging technologies essential for integrating multiple chiplets. 2.5D packaging places dies side-by-side on a passive silicon interposer, which provides ultra-high-density wiring between them. 3D packaging stacks dies vertically using through-silicon vias (TSVs) for even shorter, faster interconnects. These techniques are the physical enablers of chiplet architectures, replacing the need for a monolithic die by allowing heterogeneous components (e.g., CPU, GPU, I/O, HBM) to be assembled into a single, high-performance package.

An open industry standard defining the physical layer, protocol stack, and software model for die-to-die interconnects. UCIe aims to create an ecosystem where chiplets from different manufacturers can interoperate, similar to how PCI Express works for board-level components.

• Key Goal: To establish a plug-and-play ecosystem for chiplets, reducing vendor lock-in.
• Layers: Specifies the physical layer (bumps, channels), die-to-die adapter, and protocol layers (mapping to PCIe or CXL).
• Impact: Critical for the long-term viability of a multi-vendor chiplet market.

The on-die communication fabric that manages data traffic between intellectual property (IP) blocks, including chiplets, within a package. In a chiplet system, a NoC acts as the scalable interconnect backbone, replacing traditional shared buses.

• Function: Routes data packets between processor cores, memory controllers, and I/O chiplets.
• Advantage: Provides higher bandwidth and better scalability than bus-based architectures, which is essential for coordinating multiple chiplets.
• Analogy: The "network switch" inside the chip package.

A thin slice of silicon embedded within a 2.5D package that provides the electrical interconnection between chiplets. It is a passive layer containing a dense mesh of microscopic wiring (interconnect fabric).

• Role: Sits beneath the chiplets, offering short, fast, and energy-efficient communication paths compared to traditional off-package links.
• Material: Typically made of silicon, enabling very fine wiring pitch.
• Benefit: Allows for high-bandwidth memory (HBM) stacks to be placed extremely close to compute chiplets, drastically reducing latency.

The design methodology of assembling disparate semiconductor components—manufactured on different process nodes or with different technologies—into a single, tightly coupled package. Chiplet architecture is the primary implementation of this concept.

• Core Principle: "Right tool for the job." Optimizes cost and performance by combining a leading-edge logic chiplet (e.g., 3nm CPU) with older-node, larger, or specialized chiplets (e.g., 28nm analog I/O, GaN power, or photonics).
• Contrast with Monolithic: Avoids the yield and cost penalties of building everything on a single, massive, advanced-node die.

A broader packaging approach where multiple integrated circuits (ICs), passive components, and potentially antennas or sensors are enclosed in a single package to form a complete system or major subsystem. Chiplet-based designs are a sophisticated type of SiP.

• Scope: Can include monolithic dies, chiplets, MEMS, and discrete components.
• Relation to Chiplets: While all chiplet systems are SiPs, not all SiPs use chiplet architecture. Chiplets imply a modular, interoperable design philosophy for the silicon dies themselves.
• Example: A smartphone module containing an SoC, DRAM, flash memory, and power management IC in one package is an SiP.