Direct RF Sampling

The defining characteristic of this architecture is the removal of the superheterodyne stage. Instead of mixing the RF signal with a local oscillator to create an intermediate frequency (IF), the signal is digitized directly at the carrier frequency. This eliminates IQ imbalance, LO leakage, and flicker noise associated with analog mixers, dramatically simplifying the RF front-end design and reducing component count.

Direct RF sampling intentionally exploits aliasing by using a sample rate lower than twice the carrier frequency but higher than twice the signal bandwidth. The high-frequency signal is folded down into a lower Nyquist zone through intentional subsampling. This acts as a natural digital down-converter, translating the RF signal to a lower frequency without any analog mixing. The ADC must have sufficient analog input bandwidth to capture the high-frequency carrier.

The architecture is extremely sensitive to aperture jitter on the sampling clock. Because the signal is being digitized at a high carrier frequency, the slope of the waveform is very steep. A tiny timing error in the clock edge translates into a large voltage error, directly degrading the Signal-to-Noise Ratio (SNR). This demands ultra-low phase noise clock sources and meticulous clock distribution design.

The ADC outputs a massive, continuous stream of raw data at multi-GSPS rates. This necessitates a high-throughput digital pipeline, typically implemented on an FPGA or custom ASIC. The first digital task is often a channelizer—a polyphase filter bank or FFT-based algorithm—that splits the wideband spectrum into hundreds of narrowband sub-channels for parallel, lower-rate processing by subsequent DSP blocks.

Without narrowband analog filters or fixed local oscillators, the receiver's instantaneous bandwidth is limited only by the ADC's analog input bandwidth and sample rate. The system can monitor or intercept signals across multiple, non-contiguous frequency bands simultaneously. Changing the center frequency is a purely digital operation, allowing for near-instantaneous retuning and true software-defined radio flexibility.

Digitizing the entire spectrum means the ADC must simultaneously handle a weak signal of interest and a strong adjacent blocker without clipping. This requires an ADC with an exceptionally high Spurious-Free Dynamic Range (SFDR). The lack of analog pre-filtering places the entire burden of selectivity on the digital domain, demanding high-resolution converters and robust digital linearization techniques like Digital Pre-Distortion (DPD).

The core digital process following the ADC in a direct RF sampling receiver. A DDC translates a digitized signal from a high sample rate to a lower, complex baseband representation. This is achieved through a cascade of a numerically controlled oscillator (NCO) mixer, a decimation filter, and a sample rate converter. The primary goal is to isolate a specific channel of interest from the wideband input while reducing the data rate to a level manageable by a baseband processor.

The critical serial communication link between a high-speed ADC and a digital processing device like an FPGA. Direct RF sampling generates massive data throughput, often exceeding 100 Gbps, which cannot be handled by parallel LVDS interfaces. JESD204C provides a multi-lane, high-speed serial protocol supporting up to 32 Gbps per lane with deterministic latency. Key features include:

• 8b/10b or 64b/66b encoding for DC balance and clock recovery.
• Subclass 1 for deterministic latency, crucial for multi-channel phase coherency.
• Scrambling to reduce electromagnetic interference (EMI).

An efficient computational structure for dividing a wideband digitized signal into multiple, equally-spaced narrowband sub-bands. Instead of implementing many individual DDCs, a polyphase filter bank decomposes a single prototype low-pass filter into polyphase components and uses a Fast Fourier Transform (FFT) to perform channelization. This architecture is ideal for applications requiring simultaneous monitoring of many channels, such as SIGINT and satellite transponders, as it dramatically reduces the required multiply-accumulate operations per second.

A primary performance metric for the ADC in a direct RF sampling system. SFDR is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component, expressed in dBc or dBFS. High SFDR is essential for detecting weak signals in the presence of strong interferers without the receiver's own non-linearities creating false targets. Direct RF sampling ADCs must maintain excellent SFDR across a wide input bandwidth, which is challenged by clock jitter and amplifier harmonics.

A digital compensation technique critical for Zero-IF and direct-conversion architectures, but also relevant for direct RF sampling systems that use quadrature digital down-conversion. Mismatches in gain and phase between the in-phase (I) and quadrature (Q) paths create an unwanted image signal that falls directly on top of the desired signal. Digital correction algorithms estimate these mismatches using statistical properties of the signal or pilot tones and apply a complex filter to cancel the image, often improving image rejection from 30 dB to over 60 dB.

A system design property guaranteeing a fixed, known delay from the antenna input to the digital output. This is non-negotiable for applications like beamforming, direction finding, and TDOA geolocation, where phase coherency across multiple channels must be maintained. Achieving deterministic latency in a direct RF sampling system requires:

• A JESD204C Subclass 1 interface with a precise SYSREF signal.
• A fixed, known processing pipeline in the FPGA with no variable buffering.
• A global synchronization mechanism to align data across multiple converter chips.