CORDIC Algorithm

CORDIC replaces complex function evaluation with a sequence of micro-rotations.

• Each iteration rotates a vector by a fixed, pre-computed angle stored in a lookup table.
• The rotation angle for step i is atan(2^{-i}), allowing the multiplication by the tangent to be implemented as a simple binary right-shift.
• The algorithm operates in one of two modes: Rotation Mode (driving the angle accumulator to zero) or Vectoring Mode (driving the Y-coordinate to zero).
• Convergence is guaranteed for angles within approximately ±99.7° for circular CORDIC.

CORDIC is a unified algorithm that computes different function classes by changing a single parameter m in the iteration equations:

• Circular (m=1): Computes sine, cosine, arctangent, and vector magnitude. The fundamental mode for digital down-conversion and FFT twiddle factor generation.
• Linear (m=0): Performs multiplication, division, and linear coordinate transforms without a hardware multiplier.
• Hyperbolic (m=-1): Computes hyperbolic sine, cosine, arctanh, natural logarithm, and exponential functions.

This unification allows a single hardware core to serve multiple DSP functions.

CORDIC's primary value in FPGA and ASIC designs is the elimination of embedded multipliers and block RAM for elementary function generation.

• A fully pipelined CORDIC core uses only registers, adders, and barrel shifters.
• Latency equals the number of iterations (typically 12-16 for single-precision accuracy), but throughput can reach one result per clock cycle after pipeline fill.
• Compared to a lookup-table with linear interpolation, CORDIC consumes significantly fewer block RAM resources for high-precision angle generation.
• The regular, repetitive structure maps efficiently to FPGA logic slices and supports high clock frequencies.

Each CORDIC micro-rotation extends the vector length by a factor of 1/cos(atan(2^{-i})). The product of these extensions across all iterations converges to a constant scale factor K ≈ 1.64676 for circular CORDIC.

• In Rotation Mode, the output coordinates must be multiplied by 1/K to restore the correct magnitude.
• This correction can be absorbed into subsequent processing stages or implemented as a constant-coefficient multiplier.
• In Vectoring Mode, the computed magnitude is already scaled by K, requiring the same compensation.
• Some implementations pre-scale the initial values to avoid a post-correction multiplication.

CORDIC implementations trade off resource usage against throughput:

• Iterative (Folded): A single CORDIC stage is re-used sequentially, controlled by a state machine. Minimal logic area but requires N clock cycles per result. Suitable for low-sample-rate applications.
• Fully Pipelined (Unrolled): Each iteration is instantiated as a dedicated hardware stage. Produces a new result every clock cycle at the cost of N times the logic. Ideal for wideband DDC and real-time NCO applications.
• Hybrid: Partially unrolled designs balance area and throughput by grouping multiple iterations per pipeline stage.

CORDIC is the standard method for implementing Numerically Controlled Oscillators (NCOs) in wideband DDC chains.

• A phase accumulator generates a linearly increasing angle, and the CORDIC core in circular rotation mode simultaneously produces the corresponding sine and cosine values.
• This generates the complex local oscillator signal required to mix an input signal to baseband.
• The technique inherently maintains quadrature balance between I and Q outputs, avoiding the IQ imbalance issues of separate sine/cosine lookup tables.
• Spurious-Free Dynamic Range (SFDR) is determined by the phase accumulator width and the number of CORDIC iterations.